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A circuit for preventing pull-down current reduction of sram storage unit

A memory cell and current-pulling technology, applied in the field of memory, can solve the problems of sacrificing SRAM speed and blocking

Active Publication Date: 2019-08-30
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, increasing the bit line discharge time is one of the ways to overcome this problem, but it is forced to sacrifice the speed of SRAM
The random phase difference of the dual clocks also prevents many traditional read enhancement techniques from being applied to dual-port SRAMs

Method used

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  • A circuit for preventing pull-down current reduction of sram storage unit
  • A circuit for preventing pull-down current reduction of sram storage unit
  • A circuit for preventing pull-down current reduction of sram storage unit

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Embodiment Construction

[0038] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0039] In a preferred embodiment, as figure 1 As shown, a circuit that prevents the pull-down current of the SRAM memory cell from being reduced is proposed. The source end of the pull-down NMOS transistor of each of the memory cells in the same column of the SRAM is commonly connected to a source line 140, and each of the source lines can be ground wire, the circuit can include:

[0040] The address detection module 110 is provided with an address interface for receiving the address of the target storage unit; the address detection module 110 generates an address matching signal according to the address; the address detection module 110 block is also provided with an address matching an output port for outputting the address matching signal;

[0041] The negative pressure generating module 120 is connected to the address detection module 110 to rece...

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PUM

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Abstract

The invention relates to the field of memory, in particular to a circuit for preventing the drop-down current of an SRAM storage unit from decreasing, including an address detection module, a negative voltage generation module and a negative voltage distribution module, and the address detection module is provided with an address interface for receiving The address of the target storage unit; the address detection module generates an address matching signal according to the address, and the address detection module is also provided with an address matching output port for outputting the address matching signal, and the negative pressure generation module is connected with the address detection module to Receive and control the negative pressure generation module to generate a negative pressure signal according to the address matching signal, and the negative pressure distribution module is respectively connected with the negative pressure generation module and the source line to receive the negative pressure signal, and distribute the negative pressure signal to each source line While disconnecting each source line from the ground, thereby increasing the pull-down current of the source line.

Description

technical field [0001] The invention relates to the field of memory, in particular to a circuit for preventing the pull-down current of an SRAM storage unit from decreasing. Background technique [0002] When dual-port SRAM (Static Random Access Memory, static random access memory) double-reads the same storage unit, or double-reads different storage units in the same row, or reads and writes different storage units in the same row. Read margins can deteriorate rapidly. The reason is that the generation of the derivative read phenomenon will seriously reduce the pull-down current of the memory cell, which is very harmful to the low-voltage operation of the SRAM. [0003] At present, increasing the discharge time of the bit line is one of the ways to overcome this problem, but it is forced to sacrifice the speed of the SRAM. The random phase difference of the dual clocks also prevents many traditional read enhancement techniques from being applied to dual-port SRAMs. Cont...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/418G11C11/419
Inventor 王礼维
Owner WUHAN XINXIN SEMICON MFG CO LTD