A circuit for preventing pull-down current reduction of sram storage unit
A memory cell and current-pulling technology, applied in the field of memory, can solve the problems of sacrificing SRAM speed and blocking
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[0038] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0039] In a preferred embodiment, as figure 1 As shown, a circuit that prevents the pull-down current of the SRAM memory cell from being reduced is proposed. The source end of the pull-down NMOS transistor of each of the memory cells in the same column of the SRAM is commonly connected to a source line 140, and each of the source lines can be ground wire, the circuit can include:
[0040] The address detection module 110 is provided with an address interface for receiving the address of the target storage unit; the address detection module 110 generates an address matching signal according to the address; the address detection module 110 block is also provided with an address matching an output port for outputting the address matching signal;
[0041] The negative pressure generating module 120 is connected to the address detection module 110 to rece...
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