MOS transistor and forming method thereof
A MOS transistor and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of poor performance and reliability of MOS transistors, achieve the effect of reducing junction capacitance, reducing punch-through effect, and increasing vertical depth
Active Publication Date: 2016-12-07
SEMICON MFG INT (SHANGHAI) CORP
View PDF3 Cites 7 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
[0004] MOS transistors formed with prior art techniques suffer from poorer performance and reliability as feature sizes shrink further
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0035] The performance and reliability of the MOS transistors formed in the prior art are poor as the feature size is further reduced.
[0036] Figure 1 to Figure 4 It is a schematic cross-sectional structure diagram of the formation process of a MOS transistor according to an embodiment of the present invention.
[0037] refer to figure 1 , providing a semiconductor substrate 100, forming a gate structure 110 on the surface of the semiconductor substrate 100, the gate structure 110 including a gate dielectric layer 111 on the surface of the semiconductor substrate 100 and a gate electrode layer 112 on the surface of the gate dielectric layer 111 .
[0038] refer to figure 2, forming offset spacers 121 on the sidewall surface of the gate structure 110, using the offset spacers 121 and the gate structure 110 as a mask, lightly doping the semiconductor substrate 100 on both sides of the gate structure 110 Lightly Doped Drain (LDD) implantation to form a lightly doped regio...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention provides an MOS transistor and a forming method thereof. The forming method of the MOS transistor comprises the steps that a semiconductor substrate is provided; a gate structure is arranged on the surface of the semiconductor substrate; offset side walls are arranged at two sides of the gate structure; lightly doped drain injection is carried out on the semiconductor substrate at two sides of the gate structure to form lightly doped regions; a gap side wall is formed on the surface of each offset side wall; source-drain regions are formed on the semiconductor substrate at two sides of the gate structure; barrier layers are formed on the surfaces of the source-drain regions and are used for preventing ions from being implanted into the source-drain regions; the offset side walls and the gap side walls are removed by employing an etching process to form openings; and first halo implantation is carried out on the semiconductor substrate exposed from the openings to form first halo regions. By the forming method of the MOS transistor, the performance of the MOS transistor can be improved.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a MOS transistor and a forming method thereof. Background technique [0002] MOS (Metal-Oxide-Semiconductor) transistor is one of the most important elements in modern integrated circuits. The basic structure of MOS transistors includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and the gate structure includes : the gate dielectric layer on the surface of the semiconductor substrate and the gate electrode layer on the surface of the gate dielectric layer; the lightly doped region on the semiconductor substrate on both sides of the gate structure and the source and drain on the semiconductor substrate on both sides of the gate structure Area. [0003] The method for forming the MOS transistor is: providing a semiconductor substrate, forming a gate structure on the surface of the semiconductor substrate, the gate s...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/31H01L21/336
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP