Storage member and manufacture method

Abstract

The invention discloses a storage unit and a manufacture method. The storage member comprises a substrate, a plurality of lamination structures, a plurality of conducting columns, a plurality of charge storage layers and a plurality of third conductor layers; the lamination layer structures are arranged on the base; the lamination layer structures are arranged along a first direction and extended along a second direction, wherein each lamination structure comprises a plurality of conducting layers and a plurality of dielectric layers which are alternatively laminated along a third direction; each conducting column is arranged on the base between the two adjacent lamination structures; each charge storage layer is positioned between the lamination layer structure and the conducting column; each third conducting layer is extended along the first direction, is intersected with the lamination structures in multiple intersection areas and covers part of the lamination structures and the tops of the conducting columns; and each intersection area of the lamination structure and the third conducting layer has an air gap and the air gap is extended along a third direction.

Description

technical field [0001] The present invention relates to a semiconductor element and its manufacturing method, and in particular to a memory element and its manufacturing method. Background technique [0002] As technology advances with each passing day, advances in electronic components have increased the need for greater storage capacity. To increase storage capacity, memory elements have become smaller and more densely packed. Therefore, the three-dimensional memory element has gradually drawn great attention from the industry. [0003] However, as the size of the storage device becomes smaller and the integration level increases, the capacitance effect between the word line and the bit line becomes more and more obvious, and the program disturbance caused by it may affect the storage device. performance of a cell or memory cell array. Therefore, how to reduce the capacitive effect between the word line and the bit line, so as to avoid the interference phenomenon caused...

AI Technical Summary

Problems solved by technology

[0003] However, as the size of the storage device becomes smaller and the integration level increases, the capacitance effect between the word line and the bit line becomes more and more obvious, and the program disturbance caused by it may affect the storage device. performance of a cell or memory cell array

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