A circuit layout structure

Abstract

The invention discloses a circuit layout structure, which includes an inter-metal dielectric layer surrounding metal interconnects and a metal pattern located in a cutting lane. The scribe lines are adjacent to the IMD layer and the metal interconnects, and the metal interconnects or metal patterns are appropriately isolated to reduce capacitive effects.

Description

[0001] This application is a divisional application of an invention patent application with a filing date of November 23, 2009, an application number of 200910225937.8, and an invention title of "a circuit layout structure". technical field [0002] The invention relates to a circuit layout structure. In particular, the present invention relates to a special circuit layout structure. In these circuit layout structures, the metal interconnection surrounded by the inter-metal dielectric layer is properly isolated from the metal pattern in the scribe line, so as to reduce the undesirable capacitance effect. Background technique [0003] During the manufacture of semiconductor devices, etching processes are often used to create predetermined patterns in predetermined material layers. Figure 1-Figure 3 Illustrative of the process of using conventional etching procedures to create a predetermined pattern in a predetermined material layer in the known art. First, please refer to ...

AI Technical Summary

Problems solved by technology

Due to the static electricity generated by the electrostatic device, it is likely to induce the conductive metal mask 130 through the substrate 101, such as a titanium nitride mask, and induce the metal pattern 114 located in the scribe line 103 to form an unfavorable capacitance. , and then attract too much charged etching residue to accumulate in the bottom of the trench 121 in the chip region 102, and then the metal contact plug 111 under it cannot be exposed, and the electrical connection cannot be effectively formed.

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