Semiconductor device and method of forming the same

Abstract

The invention discloses a semiconductor device and a formation method thereof. The formation method of the semiconductor device comprises the steps of providing a substrate, forming a resistance region in first fin parts, forming an isolating layer on the surface of the substrate, forming a gate structure spanning the first fin parts, and forming source regions and drain regions in a well region of the first fin parts on the two sides of the gate structure, wherein the first fin parts are arranged on the surface of the substrate; the well region is arranged in the first fin parts and the substrate; second type ions are arranged in the well region; first type ions are arranged in the resistance region; the isolating layer covers partial side walls of the first fin parts; the surface of the isolating layer is lower than the top surfaces of the first fin parts; the gate structure covers the side walls and the top surfaces of the partial first fin parts and the surface of the partial isolating layer; first type ions are arranged in the source regions and the drain regions; and the drain regions are connected with the resistance region. The performance of the semiconductor device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] As semiconductor chips are used more and more widely, there are more and more factors that cause semiconductor chips to be damaged by static electricity. In existing chip designs, electrostatic discharge (ESD, Electrostatic Discharge) protection circuits are often used to reduce chip damage. The design and application of existing electrostatic discharge protection circuits include: gate grounded N-type field effect transistor (Gate Grounded NMOS, GGNMOS) protection circuit, silicon controlled rectifier (Silicon Controlled Rectifier, SCR) protection circuit, lateral diffusion field effect transistor ( Laterally Diffused MOS, LDMOS) protection circuit, etc. [0003] figure 1 It is a schematic cross-sectional structure diagram of an existing gate-grounded N-type field effect tra...

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Problems solved by technology

However, as semiconductor devices are further reduced in size, performance remains unstable even when FinFETs are used in ESD protection circuits

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