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On-chip parallel SerDes system and implementation method

A technology of parallelizer and system clock, which is applied in the system field of on-chip SerDes technology, can solve the problems of insufficient GPU bandwidth, achieve high storage bandwidth, improve data bandwidth, and save wiring space resources

Inactive Publication Date: 2017-01-18
长沙中部芯空微电子研究所有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In fact, the GPU bandwidth has exceeded the CPU bandwidth by many times. In the latest design, it has exceeded 190GB / s, but it is still insufficient, and it is still far from meeting the requirements of the application requirements for the GPU bandwidth.

Method used

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  • On-chip parallel SerDes system and implementation method
  • On-chip parallel SerDes system and implementation method
  • On-chip parallel SerDes system and implementation method

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Embodiment Construction

[0028] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] like figure 1 As shown, a top-level topology diagram of an on-chip parallel SerDes system of the present invention. Including: data sending end 1, complete data parallel to serial conversion; data receiving end 2, complete data serial conversion to parallel; serial parallel clock generator 3, generate 16-phase clock clk- SerDes1--clk-SerDes16. Wherein, the data sending end 1 converts the input 16-bit parallel data d15-d0 into serial data d0, d1, . . . , d15 under the control of the system clock sclk, and sends them out. Send d0 first, then d1, and finally d15. The data receiver 2 converts the received serial data d0, d1,...,d15 into parallel data d15-d0 under the control of the system clock sclk, and then sends them out. The system clock sclk is responsible for the clock synchronization of the sending end and the receiving ...

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Abstract

The invention discloses an on-chip parallel SerDes system and an implementation method. The system comprises a data transmitting end (1) and a data receiving end (2), wherein the data transmitting end (1) converts parallel data into serial data under the control of a system clock sclk and then transmits the serial data to the data receiving end (2); the data receiving end (2) converts the received serial data into parallel data under the control of the system clock sclk. A large amount of data, addresses and control buses are subjected to data transmission by a parallel SerDes technology method, so that the wiring space resource is greatly saved and technical basis is provided for further increasing data bandwidth of GPU. According to the method, the structure is simple, the storage bandwidth is high and the data transmission efficiency can be greatly improved.

Description

technical field [0001] The present invention relates to SerDes technology, in particular to a system and a realization method of on-chip SerDes technology. Background technique [0002] With the increasing application of high-speed image processing technology, the performance requirements for images are also increasing. [0003] high. With the hard work of hardware designers, the rapid development of image processing from single-core processor system to multi-core technology has provided a new research direction and solution for parallel processing of high-speed images. Software designers have accelerated some applications by more than 100 times, but only after the enhanced algorithms have been heavily optimized and tuned so that more than 99.9% of the execution time of the application is spent in the parallel execution part. In general, direct parallelization of an application may saturate the memory (DRAM) bandwidth, resulting in a speedup of only 10x. The solution lies...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
CPCG06F13/387G06F2213/0002G06F2213/0004G06F2213/3852
Inventor 胡封林李剑川
Owner 长沙中部芯空微电子研究所有限公司
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