Multi-chip stacked package structure and manufacture method thereof

Abstract

The invention provides a multi-chip stacked package structure and a manufacture method thereof. The package structure comprises a package substrate, a number of chips and a number of flexible substrates. One of the chips is surface-mounted on the package substrate through a solder ball or bump. The remaining chips are surface-mounted on the flexible substrates through solder balls or bumps respectively. The flexible substrates with the surface-mounted chips are sequentially stacked and fixed on other chips through glue. The chip stacked structure is realized. Pads aligned up and down are arranged on the flexible substrates. After the flexible substrates are bent, the pads on the flexible substrates are aligned with pads on the package substrate. The pads on the flexible substrates and the pads on the package substrate are welded together, so that the flexible substrates and the package substrate are fixed together. All chips are connected, and the chips and the package substrate are connected. According to the invention, a number of chips are stacked and packaged, and the multi-chip stacked package structure and the manufacture method thereof have the advantages of simple process, high reliability and low cost.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a multi-chip stack packaging structure and a manufacturing method thereof. Background technique [0002] With the development of integrated circuit technology, the packaging technology of integrated circuits is also constantly improving, and its development direction is mainly towards the diversified development of light, thin, short and small, and the requirements for integration are getting higher and higher; More chip devices are integrated in a given space. This demand has promoted the continuous development of three-dimensional packaging technology, and chip stacking, TSV (Through silicon via, penetrating silicon via) technology, CSP (Chip scale package, chip-level packaging) and WLP (Wafer level packaging, wafer packaging) have emerged. Round-level packaging) is the representative advanced packaging form. As a kind of three-dimensional packaging, chip stac...

AI Technical Summary

Problems solved by technology

[0004] With the continuous improvement of integration, when the number of stacked chips is large, using the solution of patent 1 to realize three-dimensional packaging will bring great process difficulty and reliability problems

At the same time, limited by the number of solder ball reflows, patent 2 also cannot realize the stacking of too many packages, generally not more than 2

Although patent 3 and patent 4 can easily realize multi-chip three-dimensional stacking and efficient interconnection, the process is complex, the reliability is not high, and the cost is high

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