Isolated ldmos structure and manufacturing method thereof

An isolation type, isolation trench technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of not completely improving the electric field distribution of the device, the contradiction between the device withstand voltage and on-resistance, etc., and achieve process implementation. Difficulty reduction, optimized breakdown voltage relationship, effect of preventing mutual crosstalk

Active Publication Date: 2019-08-02
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this type of structure cannot completely improve the electric field distribution in the device body, and there is still a contradiction between the device withstand voltage and on-resistance

Method used

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  • Isolated ldmos structure and manufacturing method thereof
  • Isolated ldmos structure and manufacturing method thereof
  • Isolated ldmos structure and manufacturing method thereof

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Embodiment Construction

[0035] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] An isolated LDMOS structure, including an isolation trench structure and an LDMOS structure integrated on the same P-type substrate 5; the isolation trench structure is located in the second P-type heavily doped region 11 and the P-type diffused well region of the LDMOS structure Inside the P-type substrate 5 between 7, the isolation groove structure includes at least one groove 2, a filling medium inside the groove 2, a first P...

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Abstract

The invention provides an isolated LDMOS structure and a manufacturing method thereof, comprising an isolation groove structure and an LDMOS structure integrated on the same P-type substrate substrate; the isolation groove structure is located in the second P-type heavily doped region and the P-type Inside the P-type substrate between the diffusion well regions, the isolation trench structure includes at least one trench, the filling medium inside the trench, the first P region at the bottom of the trench, the first oxide layer at the edge of the trench, and the upper surface of the trench is the third layer of LDMOS. Oxide layer; the present invention implants semiconductor impurities of the same doping type as the substrate material at the bottom of the isolation trench to solve the problem of premature breakdown on the surface of the source end and further improve the breakdown voltage. At the same time, the trench isolation helps to suppress the lateral Expanding and reducing the size of the device area, the invention changes the electric field distribution close to the source end, increases the doping concentration in the drift region, thereby increasing the withstand voltage of the device and reducing the specific on-resistance, and further optimizes the relationship between the specific on-resistance and the breakdown voltage.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to an isolated LDMOS structure and a manufacturing method thereof. Background technique [0002] LDMOS (Lateral Double-Diffused MOSFET) is a commonly used semiconductor device, which has the advantages of high power gain, high efficiency and low cost, and is widely used in semiconductor technology. In order to improve the LDMOS breakdown voltage and increase the output power, the method of increasing the length of the drift region and reducing the doping concentration of the drift region is usually used, which will lead to an increase in the specific on-resistance of the device and increase power consumption. Since the introduction of RESURF technology and slot isolation technology, improved structures such as Single-RESURF LDMOS, Double RESURF LDMOS, Triple RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURFLDMOS, and SJ LDMOS have had a significant effect on reducing...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/0611H01L29/66681H01L29/7816
Inventor 乔明程诗康方冬张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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