104results about How to "Reduce surface electric field" patented technology

The present invention provides a p-i-n-(-n)-type GaN single-photon avalanche detector. The detector comprises a p-GaN upper contact layer, an i-GaN avalanche multiplication layer, an n<->-GaN hole-injection layer and an n-AlGaN lower contact layer arranged from up to down, wherein the n<->-GaN hole-injection layer is light doping. The p-i-n-(-n)-type GaN single-photon avalanche detector replaces an n-GaN layer with a traditional pin-type structure with the n<->GaN/n-AlGaN heterojunction, takes the n<->-GaN as an absorption injection layer, and takes the n-AlGaN as the lower contact layer so as to facilitate the improvement of the crystalline quality of epitaxial materials of an active region and improve the external quantum efficiency and the cavity minority carrier injection efficiency; and moreover, the parameters, such as doping concentration, thickness and the like, of the n<->-GaN layer are flexible and adjustable, and a very high avalanche gain can be obtained under the low work bias through compromise optimization.

The invention relates to a semiconductor device, an n-type MOS transistor and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate, a grid medium layer, a grid electrode, side walls, a light doping source/drain region, a heavy doping source/drain region, and a fluorine ion implantation region, wherein the gird medium layer, the grid electrode and the side wall are positioned inside an input/output device region of the semiconductor substrate; the low doping source/drain region and the heavy doping source/drain region are positioned inside semiconductor substrates in an n-type MOS transistor region and a p-type MOS transistor region of the input/output device region; and the fluorine ion implantation region is positioned inside a semiconductor substrate in the n-type MOS transistor region of the input/output device region. Correspondingly, the invention also provides a method for manufacturing the semiconductor device, the n-type MOS transistor and the method for manufacturing the n-type MOS transistor. The fluorine ion implantation region is formed in the low doping source/drain region of the n-type MOS transistor region, and fluorine ions in the fluorine ion implantation region and silicon in the semiconductor substrate form fluorine-silicon groups so as to prevent the formation of charge traps, prevent the aggregation of charges in the low doping source/drain region under the condition of additional voltage, and forming hot carrier effect.

The invention provides a semiconductor device with a super junction structure. The semiconductor device comprises an N-type doped semiconductor substrate and an N-type doped epitaxial layer, wherein the N-type doped semiconductor substrate and the N-type doped epitaxial layer are sequentially arranged from bottom to top, and a first P-type filling well region, a second P-type filling well region and a third P-type filling well region are arranged inside the N-type doped epitaxial layer. A first P-type doping region is arranged on the upper side of the first P-type filling well region and provided with an N-type doping region, and a second P-type doping region is arranged on the upper side of the second P-type filling well region. A terminal pressure-withstanding structure T is arranged on the periphery of a primitive cell source electrode region C, wherein the terminal pressure-withstanding structure T comprises the second P-type filling well region, the second P-type doping region, the third P-type filling well region and the corresponding part of the N-type doped epitaxial layer, and the primitive cell source electrode region C comprises the first P-type filling well region, the first P-type doping region, the N-type doping region and the corresponding part of the N-type doped epitaxial layer. The parts, corresponding to polycrystalline silicon arranged in a part of dielectric layer above a gate oxide layer, of the terminal pressure-withstanding structure T and the primitive cell source electrode region C form a gate electrode structure and a polycrystalline silicon field plate structure respectively.

The invention relates to the technical field of semiconductors, and provides a lateral double-diffused metal oxide semiconductor field effect transistor and a manufacturing method thereof. The lateral double-diffused metal oxide semiconductor field effect transistor comprises a substrate, a gate region, a source region, a drain region, a P-type body region, and an N-type well region, a P-type well region and an N-type drift region which are positioned on the substrate, and further comprises a P-type drift region formed by ion implantation, wherein the P-type drift region is located in the N-type well region, and a preset distance exists between the P-type drift region and the P-type body region. According to the invention, the P-type drift region is added in the N-type well region, the contact surface of the P-type drift region and the N-type well region forms a PN junction, and the P-type drift region and the N-type drift region form a dual RESURF structure, so that the surface electric field of the device is reduced, higher breakdown voltage can be borne, and lower on-resistance can be maintained.

The invention discloses a high-sided transverse double diffused field effect transistor. The high-sided transverse double diffused field effect transistor comprises a P type substrate, an N- epitaxial layer, a P+ buried layer, a P+ P-N junction isolation, field oxygen, a P- top layer, P- body areas, a P- body area contact P+, an N+ source electrode, a gate oxygen layer, a polycrystalline silicon gate electrode and an N+ drain electrode, wherein the N- epitaxial layer is arranged above the P type substrate; the P+ buried layer and the P+ P-N junction isolation are arranged at one side of the N- epitaxial layer and are used to isolate different types of devices; furthermore, another P- body area is arranged between the P- body area and the P+ P-N junction isolation; the body area contact P+ is arranged in the P- body area; the P- top layer is arranged between the P- body area and the another P- body area. According to the high-sided transverse double diffused field effect transistor disclosed by the invention, an avalanche breakdown voltage between the source electrode and the substrate is greatly increased, that is, an isolation performance is greatly improved, so that application in the field which requires relatively high working voltage is satisfied.

The invention discloses an ESD (electrostatic discharge) high-voltage DMOS (diffused metal oxide semiconductor) device which comprises an ESD ion injection region, wherein the ESD ion injection region is formed in part of a drift region under a field oxide layer, impurity ions are injected into a buried layer and enter into the drift region by annealing, propelling and diffusing, and the ESD ion injection region has impurity distribution with gradually reduced concentration between the buried layer and the bottom of the field oxide layer. The invention further discloses a manufacturing methodof the ESD high-voltage DMOS device. By adopting the device and the manufacturing method, the trigger voltage of the device can be effectively reduced, the resistance of the drift region and the on-resistance of the device can be reduced, the strength of a surface electric field of the drift region can be reduced, and a gate oxide can be protected.

The invention relates to a terminal structure of a metal oxide semiconductor field effect transistor (MOSFET). The terminal structure comprises an N-type cut-off ring and further comprises a first P-type low-doped region and a second P-type low-doped region, wherein the first P-type low-doped region and the second P-type low-doped region are formed between the cut-off ring and an active region through ion implantation, the implantation dose ranges from 1.5*10<11>/cm<2> to 2*10<13>/cm<2>, implantation energy ranges from 20 kilo electron volts to 80 kilo electron volts, the first P-type low-doped region is closer to the active region than the second P-type low-doped region, and the length of the first P-type low-doped region is smaller than that of the second P-type low-doped region. The invention further relates to a manufacturing method of the terminal structure of the MOSFET. The two P-type low-doped regions are adopted for reducing a surface electric field and increasing the breakdown voltage of the MOSFET, the terminal structure replaces a traditional terminal structure with a plurality of voltage dividing rings, the terminal size is greatly reduced, the effective use area of a chip is increased, and parameters of the chip are more excellent under the same area.

The invention discloses a terminal protection structure of a super junction device. The composite structure of polysilicon field plates and metal field plates is employed, and a group of polysilicon field plates and metal field plates simultaneously cover the step structure of a terminal dielectric film, thus an electric field on the device surface is eased. According to the invention, a P-type ring with a high concentration is kept under a field plate, thus the current processing capability of the application of the device in an inductive circuit is improved. In the terminal protection structure provided by the invention, the depth of a P-type column and a N-type column is lower than the depth of a P-type area and a N-type area in a current flowing area to ensure that the device is turned off when the device is applied in the inductive circuit and that the position where an avalanche breakdown occurs in the terminal protection structure is close to the position of the obverse of a silicon chip when a current overshoot occurs, and to improve the capacity of anti-overshoot current of the device. The invention further discloses the super junction device terminal protection structure and a manufacturing method thereof. According to the invention, the breakdown characteristic, the current processing capability and the reliability of the device is improved without process cost increasement.

A shallow-groove isolation structure transverse semiconductor device arranged in a staggered and interdigital way comprises a P-type substrate, wherein a high-voltage N-type region is arranged on theP-type substrate, an N-type drift region and a P-type body region are arranged on the high-voltage N-type region, an N-type drain region and three shallow-groove isolation regions are arranged in theN-type drift region, an N-type source region and a P-type region are arranged in the P-type body region, a U-shaped gate oxide layer is further arranged on the high-voltage N-type region, a U-shaped opening of the gate oxide layer faces a drain end, two ends of the gate oxide layer respectively extend to a part above the P-type body region and a part above the shallow-groove isolation regions, a poly-silicon gate field plate is arranged on the gate oxide layer, drain metal contact, source metal contact and body region metal contact are respectively arranged on upper surfaces of the N-type drain region, the N-type source region and the P-type region, and the shallow-groove isolation structure transverse semiconductor device is characterized in that the shallow-groove isolation regions are arranged in the drift region in the staggered and interdigital way. By the structure, relatively low conduction resistance can be obtained on the basis that the breakdown voltage is not changed.

The invention relates to a mounting assembly for an all-optical overvoltage sensor, and belongs to the technical field of voltage measurement. The mounting assembly comprises a sensor fixing housing, a transmission conductor expansion sleeve, a PVC hose, a polarization maintaining optical fiber patch cord disposed in the hose in a sleeving manner, an optical fiber insulator provided internally with a polarization maintaining optical fiber, and a connecting fitting. The transmission conductor expansion sleeve sleeves a transmission conductor fixedly. A sensor is mounted in the sensor fixing housing. The sensor fixing housing sleeves the transmission conductor expansion sleeve fixedly. Two ends of the PVC hose are respectively connected with the sensor fixing housing and the optical fiber insulator. Two ends of the polarization maintaining optical fiber patch cord in the PVC hose are respectively connected with a tail fiber of the sensor and the polarization maintaining optical fiber disposed in the optical fiber insulator. According to the invention, the mounting assembly can be used for fixing the sensor onto a transmission line for long term monitoring, non-electrical connection between a sensor measurement device and a power system is achieved, the safety of measurement is improved, and meanwhile, the impact of a non-measurement phase on the measurement is greatly reduced.

The invention discloses a power device JTE and buried FLR composite terminal structure and a preparation method thereof. The novel terminal structure is mainly formed by combining three structures: anupper layer of a junction terminal region of an N-type (or P-type) epitaxial voltage-withstanding layer is a P-type layer (when the epitaxy is P-type, the P-type layer is N-type) which is doped opposite to the epitaxial layer, a plurality of discrete groove rings are arranged in the upper P-type layer, and SiO2 or other High-K media are filled in grooves; a P-type ring buried field limiting ringstructure which is doped opposite to the epitaxial layer is further arranged under each groove, the upper portions of the P-type rings are connected with the P-type layer on the upper layer, and therefore the composite structure voltage-withstanding terminal with the JTE structure on the upper layer and the FLR on the lower layer is formed. The composite terminal is simple in structure and process, is not sensitive to JTE concentration or process deviation of FLR ring width and spacing and surface charges, and can greatly improve the voltage endurance capability of the device terminal and reduce the chip area of the required voltage endurance terminal.

The invention provides a method for manufacturing a terminal structure of a deep-groove super-junction metal oxide semiconductor (MOS) device, which comprises the following steps of: providing a silicon substrate, wherein deep grooves with a super-junction structure and a terminal structure are formed on the silicon substrate respectively, and the deep grooves with the terminal structure are formed closely; depositing polycrystalline silicon layers in the deep grooves, wherein the doping type of the polycrystalline silicon layers is opposite to that of the silicon substrate; diffusing doped impurities in the polycrystalline silicon layers to the silicon substrate, and forming impurity diffusion areas at the peripheries of the deep grooves; performing thermal oxidation on the silicon substrate between the polycrystalline silicon layers and the deep grooves in a terminal structure area to form oxide layers for completely filling the deep grooves, and forming a thick oxide layer in the terminal structure area; and synchronously forming a polycrystalline silicon field plate on the thick oxide layer in the terminal structure area when a polycrystalline silicon grid of the MOS device is manufactured. The field plate is formed by the polycrystalline silicon grid in the terminal structure area and is combined with the thick oxide layer, and the voltage division effect of the thick oxide layer is effectively utilized, so that the surface field of the device is reduced; and by combining the effects of a deep groove reduced surface field (RESURF) and the field plate, the pressure division effect is obvious, and the area of a terminal is reduced to a great extent.

The invention provides a full-range calibration device and method of high voltage nanosecond pulse voltage divider calibration factors to reduce the measurement deviation of nanosecond pulse voltage in a pulse power technology. According to the full-range calibration device and method, the characteristic that the calibration coefficient of a nanosecond pulse electric field measuring probe can be calibrated by devices such as a GTEM cell or a TEM cell in a large amplitude range is utilized, by correlating the nanosecond pulse voltage and the nanosecond pulse electric field, the present situation of a nanosecond pulse voltage non-standard measurement system under a high-voltage level is skillfully avoided, the calibration of the calibration coefficient of the nanosecond pulse divider under hundreds of kilovolts voltage level is achieved, and the traceability problem of hundreds of kilovolts voltage measurement in the pulse power technology is solved.

The invention relates to a power semiconductor device with a wave type field limiting ring structure. The device comprises a P-type substrate (1). An N-type buffer layer (2) is arranged on the P-typesubstrate (1). An N-type epitaxial layer (3) is arranged on the N-type buffer layer (2). The N-type epitaxial layer (3) is divided into a cell region, a transition region, and a termination region. Gate trenches (4-1) and (4-2) are formed in the cell region. Gate trenches (4-3), (4-4) and (4-5) are formed in the transition region. A P-type body region (6) is arranged between the gate trenches (4-1) and (4-2). A heavily doped N-type emitter (7) is arranged in the P-type body region (6). The device is characterized in that a wave-type overlapped ion diffusion region (10) is arranged in the terminal region; and ion implantation regions (10-1), (10-2) and (10-3) are arranged in the wave-type ion diffusion region (10). The device structure of the present invention is capable of suppressing electric field spikes generated when the device is turned off, thereby suppressing dynamic avalanche.

The invention discloses a high-voltage semiconductor component comprising a substrate, a first well region having a second conductivity type, a second well region having a first conductivity type, a first doped region, a second doped region, a gate structure and multiple isolation structures. The first well region is located on the substrate. The second well region is located on the substrate nextto the first well region. The first doped region is located in the first well region. The second doped region is located in the second well region. The gate structure is loated on the substrate between the first doped region and the second doped region. The isolation structures are located in the first well region. The isolation structures are staggered in an array. Each isolation structure includes a dielectric pillar and a top doped region below the dielectric pillar. The bottom surface of the first well region is lower than the bottom surface of each isolation structure.

The embodiment of the invention provides a production method for an enhanced GaN transistor. The method comprises the steps of growing a phosphorus-doped GaN dielectric layer, an AlGaN dielectric layer and an Si3N4 dielectric layer on the surface of a silicon substrate in sequence; etching the Si3N4 dielectric layer; depositing metal layers on the upper surfaces of the exposed AlGaN dielectric layer and the residual Si3N4 dielectric layer; carrying out dry etching downward along a predetermined area of the surface of the exposed Si3N4 dielectric layer; and depositing an SiO2 dielectric layer in a gate contact hole as gate dielectric. According to the embodiment of the invention, the phosphorus-doped GaN dielectric layer is grown on the surface of the silicon substrate and a surface electric field of the enhanced GaN transistor is reduced, so the voltage resistance is improved; and moreover, phosphorus is doped in a gate of the enhanced GaN transistor and the composition of electrons and holes exists, so the on resistance is reduced, and a technology demand that the on resistance of the GaN transistor is relatively low and the voltage resistance is relatively high is realized.

The invention discloses an laterally diffused metal oxide semiconductor (LDMOS) structure for protecting a channel district by utilizing a polysilicon field polar plate, comprising a deep trap, a source electrode, a drain electrode, a grid electrode and the channel district, wherein the source electrode, the drain electrode, the grid electrode and the channel district are in the deep trap; the source electrode and the channel district are positioned at one side of the grid electrode; the drain electrode is positioned at the other side of the grid electrode; the doping types of the source electrode, the deep trap and the drain electrode are the same; the doping types of the source electrode, the deep trap and the channel district are opposite; and the polysilicon field polar plate is arranged above the edge of the channel district and the deep trap, or the polysilicon field polar plate is arranged above the edge of a PN junction of the channel district and the drain electrode. The LDMOS structure can reduce surface electric field between an LDMOS underway and the drain electrode so as to enhance the breakdown voltage of the LDMOS.

The invention provides an LDMOS structure in an ultrahigh voltage BCD technology. The LDMOS structure is in an N-epitaxial layer on a P-substrate. Moreover, the LDMOS structure comprises: a first high voltage P type body region, which is at the N- epitaxial layer surface; two high voltage N+ injection regions, which are respectively at the first high voltage P type body region and a drain electrode position; a gate oxide and polysilicon gate, which is at the upper surface of the N-epitaxial layer and is connected with the first high voltage P type body region; an interlayer dielectric layer, which is covered on the upper surface of the N-epitaxial layer as well as is opened with windows at a source electrode position and the drain electrode position of the LDMOS structure and the polysilicon gate position; a source electrode field plate is arranged on the interlayer dielectric layer as well as is short-circuited with the first high voltage P type body region through the source electrode window; a drain source field plate, which is arranged on the interlayer dielectric layer as well as is connected with the drain electrode through the drain electrode window; and a gate field plate, which is arranged on the interlayer dielectric layer as well as is connected with the polysilicon gate through the gate window. According to the invention, the filed plates that can reduce surface electric fields and improve an overpressure resistant performance are provided; and moreover, parasitic resistance of the polysilicon gate can be substantially reduced; and gate switching frequency can be enhanced.

The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a source electrode (51) inside the second P well (34).