JTE and buried FLR composite terminal structure power device and preparation method thereof

Abstract

The invention discloses a power device JTE and buried FLR composite terminal structure and a preparation method thereof. The novel terminal structure is mainly formed by combining three structures: anupper layer of a junction terminal region of an N-type (or P-type) epitaxial voltage-withstanding layer is a P-type layer (when the epitaxy is P-type, the P-type layer is N-type) which is doped opposite to the epitaxial layer, a plurality of discrete groove rings are arranged in the upper P-type layer, and SiO2 or other High-K media are filled in grooves; a P-type ring buried field limiting ringstructure which is doped opposite to the epitaxial layer is further arranged under each groove, the upper portions of the P-type rings are connected with the P-type layer on the upper layer, and therefore the composite structure voltage-withstanding terminal with the JTE structure on the upper layer and the FLR on the lower layer is formed. The composite terminal is simple in structure and process, is not sensitive to JTE concentration or process deviation of FLR ring width and spacing and surface charges, and can greatly improve the voltage endurance capability of the device terminal and reduce the chip area of the required voltage endurance terminal.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a JTE and FLR compound terminal structure of a power device and a preparation method thereof. Background technique [0002] SiC is a wide bandgap semiconductor material that has developed rapidly in the past ten years. Compared with other semiconductor materials, such as Si, GaN and GaAs, SiC material has wide bandgap, high thermal conductivity, high carrier saturation mobility, high power density and other advantages. SiC can be thermally oxidized to form silicon dioxide, making it possible to realize power devices and circuits such as SiC MOSFET, SBD, IGBT and GTO. Since the 1990s, power devices such as SiC MOSFETs and SBDs have been widely used in switching regulated power supplies, high-frequency heating, automotive electronics, and power amplifiers. [0003] At present, in the design and fabrication process of silicon carbide power devices, especially high-vo...

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Problems solved by technology

[0004] However, due to the high surface electric field of SiC devices, in order to improve the withstand voltage, it is necessary to reduce the surface peak electric field during device design, and it is necessary to design a large number of field limiting loops.

In the design, many factors such as the number of rings, ring width, and ring spacing will affect the surface electric field distribution, and the terminals of multiple field-limiting rings occupy a large chip area, which is not conducive to increasing the current.

However, the junction terminal extension structure JTE has a figure of merit concentration, and the breakdown withstand voltage of the device terminal is sensitive to the figure of merit concentration of JTE, so the design window is small

Moreover, the junction terminal extension structure is very sensitive to surface charges, and it is easy to affect the electric field distribution on the surface of the device due to interface instability and oxide layer charges, thereby affecting the breakdown voltage and reliability of the device.

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