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Method for time sequence analysis of digital circuit design and system for time sequence analysis of digital circuit design

A timing analysis and digital circuit technology, applied in the fields of electrical digital data processing, computing, special data processing applications, etc., it can solve the problems of unable to consider timing data, unable to read ETM, unable to fully analyze ETM timing data, etc., to reduce Quantity, the effect of increasing efficiency

Active Publication Date: 2017-03-15
GLOBAL UNICHIP CORPORATION +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, currently known routing tools cannot read all the complete ETMs in a single circuit design, and can only use the first read ETM as a reference for this circuit design, and cannot take into account the timing in other ETMs data
In other words, current routing tools cannot fully analyze the timing data of all ETMs in a single circuit design

Method used

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  • Method for time sequence analysis of digital circuit design and system for time sequence analysis of digital circuit design
  • Method for time sequence analysis of digital circuit design and system for time sequence analysis of digital circuit design
  • Method for time sequence analysis of digital circuit design and system for time sequence analysis of digital circuit design

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Embodiment Construction

[0044] The extracted timing model (Extracted timing model, ETM for short) is a timing model and liberty file generated from the gate-level circuit diagram (netlist) of the chip. The ETM has the same timing behavior as the circuit diagram of the chip, and the data size of the ETM is much smaller than that of the circuit diagram, and the ETM can be used to replace the circuit diagram in hierarchical timing analysis. The arc delay of the ETM has various arc types in the ETM, and these arc delays vary with the input transition and output load of the circuit diagram. ETM is based on the circuit diagram of the block and the third-party program library (third (3) by using the STA analysis tool. rd ) party library) and other limitations, where the STA analysis tool only extracts the timing of the interface logic. In general, circuit diagrams usually have sequential circuits and combinational circuits. For ETM, sequential circuits have timing checking (e.g., setup, hold, clock gate) ...

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Abstract

The invention provides a method for time sequence analysis of digital circuit design and a system for the time sequence analysis of digital circuit design. The method for the time sequence analysis comprises the steps that integral circuit design is acquired, wherein the integral circuit design runs under multiple working modes; aiming at the working modes of the integral circuit design, multiple time sequence extraction models are generated respectively, wherein each time sequence extraction model comprises a non-chip variation part and a chip variation part; the time sequence extraction models corresponding to the working modes are integrated into a non-chip variation time sequence model and a chip variation time sequence model, wherein the chip variation part of the working modes is not considered when the non-chip variation time sequence model is generated; and according to the non-chip variation time sequence model and the chip variation time sequence model, time sequence variation of the integral circuit design can be analyzed. According to the invention, the quantity of time sequence models read by rear-end wiring tools can be greatly reduced; and efficiency and accuracy of static time sequence analysis of the wiring tools can be enhanced.

Description

technical field [0001] The present invention relates to a digital integrated circuit (Integrated circuit, IC for short) design analysis and simulation technology, and in particular to a digital circuit design timing analysis (timinganalysis) method and system thereof. Background technique [0002] In order to simplify the design complexity of digital circuits, users can use the digital circuit design program and the built-in library (library) module (model) to design the required circuit, and carry out the functional verification of the digital circuit design of the circuit, In order to judge whether the digital circuit design can successfully meet the user's functional requirements. Since the realization of the circuit structure needs to consider quite a lot of electronic circuits and electromagnetic characteristics, such as considering the placement of each component in the circuit, the influence of the line length on the signal, timing and power transmission, etc., the di...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 廖登楠傅得栒廖信雄蔡振弘蔡旻修
Owner GLOBAL UNICHIP CORPORATION
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