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UVM based CAN controller IP verifying platform

A CAN controller and verification platform technology, applied in general control systems, control/regulation systems, CAD circuit design, etc., to achieve high efficiency, facilitate coverage statistics, and avoid confusion in execution sequences.

Active Publication Date: 2017-03-15
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
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Problems solved by technology

Using the random test method, it takes a period of time to prepare the random verification environment in the early stage, and the coverage rate has not increased during this period

Method used

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  • UVM based CAN controller IP verifying platform
  • UVM based CAN controller IP verifying platform
  • UVM based CAN controller IP verifying platform

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Embodiment Construction

[0041] The present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

[0042] The architecture of the verification platform of the present invention is as follows: figure 2 As shown, the verification platform includes the top-level TOP layer, the design DUT under test, the DUT interface module interface, the test case layer test, the verification environment layer env, the register model register model, the virtual stimulus generator virtual seqencer, the register access agent bus_agent, and the sending end stimulus The sending and receiving agent tx_agent, the receiving end incentive sending and receiving agent rx_agent, the incentive generator sequencer, the incentive sending module driver, the interface monitoring module monitor, and the result comparison module scoreboard.

[0043] The TOP layer is the top layer of the verification platform, which instantiates the test case layer test of the CAN controller D...

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Abstract

The invention relates to a UVM based CAN controller IP verifying platform. The UVM based CAN controller IP verifying platform includes a top layer (TOP layer), a design DUT to be tested, a DUT interface module (interface), a test case layer (test), a verifying environment layer (env), a register model (register model), a virtual excitation generator (virtual seqencer), a register access agent (bus_agent), a transmitting end / receiving end excitation transmitting-receiving agent (tx_agent / rx_agent), an excitation generator (sequencer), an excitation sending module (driver), an interface monitoring module (monitor), and a result comparison module (scoreboard). According to the invention, a verified object selects a CAN controller IP, the verifying platform adopts the UVM to efficiently and reliably verify data transmitting and receiving of a CAN controller in different working modes at low cost.

Description

technical field [0001] The invention relates to chip function verification, in particular to a CAN controller IP verification platform based on UVM, which is used for sending and receiving data packets of the CAN controller and testing the correctness of the received data packets. Background technique [0002] In recent years, with the continuous improvement of chip integration, the functional complexity of the chip has also greatly increased. The design process of the chip is more likely to introduce errors, and the verification work has become more difficult. In integrated circuit design, verification work accounts for more than half of the entire design cycle. The functional error caused by insufficient verification is the main reason for the low success rate of the first chip release. Traditional verification technology can no longer meet the increasing verification requirements, and verification has become a bottleneck in integrated circuit design. [0003] Traditiona...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50G05B17/02
CPCG05B17/02G06F30/30
Inventor 孙维东雷淑岚胡鹏
Owner 58TH RES INST OF CETC
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