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Haar characteristic multi-processing framework human face detection system and method based on FPGA (Field Programmable Gate Array)

A face detection and multiprocessing technology, applied in instruments, character and pattern recognition, computer parts, etc., can solve the problems of slow processor operation speed and complex face feature detection algorithm.

Inactive Publication Date: 2017-03-15
HARBIN UNIV OF SCI & TECH
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  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The present invention is to solve the problem that the existing face feature detection algorithm is complex and the processor operation speed is slow, and proposes a face detection system based on FPGA-based Haar feature multi-processing architecture

Method used

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  • Haar characteristic multi-processing framework human face detection system and method based on FPGA (Field Programmable Gate Array)
  • Haar characteristic multi-processing framework human face detection system and method based on FPGA (Field Programmable Gate Array)
  • Haar characteristic multi-processing framework human face detection system and method based on FPGA (Field Programmable Gate Array)

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specific Embodiment approach 1

[0032] Specific implementation mode 1. Combination figure 1 Illustrate the present embodiment, the Haar feature multi-processing framework human face detection system based on FPGA described in the present embodiment, it comprises image storage module 1, integral image generator 2, classifier 3 and detection window scaling module 4;

[0033] The image storage module 1 is used to extract the haar feature in the range detection window of n×n in the camera acquisition image, utilize the haar feature to extract the face feature, and use the face feature to calculate the coordinates of each pixel point of the face feature; and calculate and obtain The coordinates of each pixel point of the face feature are sent out; where n is a positive integer;

[0034] Integral image generator 2 is used to receive each pixel point coordinates of facial features, utilizes integral map method according to each pixel point coordinates of facial features, calculates facial feature values; and sends ...

specific Embodiment approach 2

[0049] Specific embodiment two, this embodiment is a further description of the FPGA-based Haar feature multiprocessing architecture face detection system described in specific embodiment one, the image storage module 1 includes an image frame buffer 11 and an address generator 12,

[0050] The image frame buffer 11 is used to extract the haar feature in the range detection window of n × n in the camera acquisition image, utilizes the haar feature to extract the face feature; and sends the extracted face feature information;

[0051] Address generator 12 is used for receiving face feature information, and the face feature information that receives is stored as two-dimensional array, utilizes pixel address=(y*w+x), calculates the coordinate (x) of each pixel point of face feature , y), where w is the width of the integral map image, and sends out the coordinates of each pixel of the calculated facial features.

specific Embodiment approach 3

[0052] Specific embodiment three, this embodiment is a further description of the FPGA-based Haar feature multiprocessing architecture face detection system described in specific embodiment one, classifier 3 includes feature classifier 31, stage comparator 32 and feature training data Device 33;

[0053] The feature classifier 31 is used to receive and store the face feature value information, and compare the received face feature value P with the feature threshold A×m, and keep the face feature value P greater than the feature threshold A×m, which will be greater than the feature threshold value P The face feature value P of the threshold A×m is sent out; among them, m=1;

[0054] The stage comparator 32 is used to receive when m=2, the face feature value P greater than the feature threshold A × m, and use the received face feature value P to compare with the feature threshold A × m, and retain the face feature value P greater than the feature threshold A × m The face featur...

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Abstract

The invention provides a Haar characteristic multi-processing framework human face detection system and method based on an FPGA (Field Programmable Gate Array) and belongs to the technical field of data human face characteristic detection, aiming at solving the problems that an existing human face characteristic detection algorithm is complicated and the computing speed of a processor is low. An image storage module is used for extracting Haar characteristics in an n*n range detection window of images acquired by a camera; human face characteristics are extracted by utilizing the Haar characteristics and a coordinate of each pixel point of the human face characteristics is calculated by utilizing the human face characteristics; the obtained coordinate of each pixel point of the human face characteristics is sent to an integral image generator; the integral image generator is used for calculating human face characteristic values according to the coordinate of each pixel point of the human face characteristics by utilizing an integral image method; the calculated human face characteristic values P are sent to a classifier; and the classifier is used for comparing the received human face characteristic values P with a characteristic threshold value A*m, and the human face characteristic values P greater than the characteristic threshold value A*m are kept. The Haar characteristic multi-processing framework human face detection system and method provided by the invention are suitable for human face detection.

Description

technical field [0001] The invention belongs to the technical field of data face feature detection. Background technique [0002] Face detection plays an important role in many applications such as recognition, surveillance, video conferencing, and camera autofocus, etc. Due to a large amount of work in the field of computer vision, face detection algorithms have developed rapidly to achieve real-time detection. Viola and Jones proposed a method based on machine learning in the literature, which can achieve a relatively high frame rate while maintaining accuracy. However, this algorithm is too slow relative to traditional processors (especially on embedded platforms). Contents of the invention [0003] The present invention is to solve the problem that the existing face feature detection algorithm is complex and the processor operation speed is slow, and proposes a face detection system based on FPGA-based Haar feature multi-processing architecture. [0004] The Haar fe...

Claims

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Application Information

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IPC IPC(8): G06K9/00
CPCG06V40/166G06V40/172
Inventor 冯志进田晓华王建民
Owner HARBIN UNIV OF SCI & TECH
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