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A circuit structure for realizing message selection from two

A circuit structure and message technology, applied in electrical components, digital transmission systems, data exchange networks, etc., can solve the problems of software that cannot be processed at line speed and low reliability, and achieve easy implementation, single function, and save control resources. Effect

Active Publication Date: 2019-02-15
STATE GRID ZHEJIANG ELECTRIC POWER CO LTD SHAOXING POWER SUPPLY CO +3
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 1. In the case of large bandwidth, the software cannot process at wire speed;
[0005] 2. Low reliability

Method used

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  • A circuit structure for realizing message selection from two
  • A circuit structure for realizing message selection from two
  • A circuit structure for realizing message selection from two

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Embodiment Construction

[0026] Term explanation:

[0027] FPGA: Field-Programmable Gate Array, field programmable gate array;

[0028] ASIC: Application Specific Integrated Circuit, application specific integrated circuit;

[0029] DDR3 SDRAM: Double data rate type three SDRAM, DDR3 cache chip;

[0030] RAM: Random Access Memory, random access memory;

[0031] FIFO: First Fn First Out, first in first out storage unit.

[0032] In order to realize the two-choice processing of the message, the message must carry the group number (GROUPID) and the stream number (SEQUENCEID, SEQID for short) information. The group number GROUPID refers to the number of message groups that undergo two-select-one processing, and the messages between different group numbers are independent of each other; the stream number SEQID refers to the sequence number of the message that is processed in the same group. The main condition of the logic of the two-choice decision.

[0033] Such as Figure 2-3 As shown, a circuit structure for rea...

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Abstract

The invention discloses a circuit structure for realizing two-choice one of messages, including a two-choice one judgment logic module, a waiting judgment cache module connected with the two-choice one judgment logic module, a current SEQID cache module, and a waiting judgment cache module connected The scanning logic module, the entrance of the one-of-two decision logic module is connected to two selective receiving channels, and the messages of the two selective receiving channels come from double-sending messages of the same source device. The circuit structure for realizing message two-choice one according to the present invention adopts independent two-choose one judgment logic module and waiting judgment cache module, so that the functions of the respective modules are relatively single, which is convenient for logic circuit realization; in addition, the waiting judgment cache module adopts The form management of RAM multiplexing saves a lot of resources waiting for the control of the decision buffer module, so that the message group number of the two-choice circuit can support up to 1K (1024), or even more.

Description

Technical field [0001] The invention belongs to the technical field of smart grids, and specifically relates to a circuit structure for realizing one of two messages. Background technique [0002] In the case that some message processing bandwidth is very small, it is a relatively simple way to use software programming to complete the message selection, such as figure 1 Shown: The FPGA chip is used to provide 4 Ethernet ports, two of which are used as the entrance of the selective receiving channel, one is used as the interconnection channel between the FPGA chip and the CPU, and the other is used as the output channel of the selective receiving result. After receiving the message from the selective receiving channel, the FPGA adds a channel mark to the message by encapsulating the outer VLAN. The modified message is forwarded to the CPU through the internal interconnection port, and the upper layer software of the CPU can extract the selective receiving message from the bottom la...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/823H04L12/851H04L47/32
CPCH04L47/2483H04L47/32
Inventor 张亮杨才明李勇姚树建金乃正马平杜奇伟潘武略刘永新凌光俞芳
Owner STATE GRID ZHEJIANG ELECTRIC POWER CO LTD SHAOXING POWER SUPPLY CO
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