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Rate-adaptive storer interface circuit

A memory interface and rate adaptive technology, applied in the field of interface circuits

Inactive Publication Date: 2017-05-17
XIAN MICROELECTRONICS TECH INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, the transparent mode of the 1553B bus controller provides an interface for external memory, but because the 1553B bus speed is fixed, this interface only provides a fixed speed

Method used

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Embodiment Construction

[0021] The present invention will be further described below in conjunction with the accompanying drawings.

[0022] see figure 1 and figure 2 , the present invention includes an internal receiving synchronous circuit for receiving internal channel signals, and an interface control circuit for receiving and sending rate control module signals, the signals of the internal receiving synchronous circuit are sent to several receiving processing modules, and the signals of all receiving processing modules are sent to the first output A logic unit, the signal of the first output logic unit is sent to the memory interface through the third output logic unit; the signals of the several port control circuits are sent to several sending processing modules, and the signals of all sending processing modules are sent to the second output logic unit, The signal of the second output logic power supply is sent to the memory interface through the third output logic unit, and the output signa...

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Abstract

The invention discloses a rate-adaptive storer interface circuit. According to the rate-adaptive storer interface circuit, a purpose that sending control signals are generated according to sending rates of all channels is achieved through a sending rate control module. The rate-adaptive storer interface circuit achieves sending rate self-adaption of communication links through the sending rate control module, compared with a constant-rate interface, the sending rate is flexible and configurable, and a time-division multiplex access method is utilized to maximize efficiency and data throughput rate of a COMI interface. The rate-adaptive storer interface circuit can be applied among all the communication links and an internal storer at the same time.

Description

technical field [0001] The invention belongs to the field of interface circuits, and in particular relates to a rate-adaptive memory interface circuit. Background technique [0002] General bus control devices have an external memory interface. Because the internal storage space of the bus controller is limited, the internal storage space is expanded by providing an external memory interface connected to a single-chip memory for data processing. send and receive. For example, the transparent mode of the 1553B bus controller provides an interface for external memory, but because the 1553B bus rate is fixed, this interface only provides a fixed rate. Contents of the invention [0003] The object of the present invention is to overcome the above-mentioned disadvantages, and provide a rate-adaptive memory interface circuit with flexible and configurable sending rate. [0004] In order to achieve the above object, the present invention includes an internal receiving synchrono...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10
CPCG11C7/1048
Inventor 刘欢
Owner XIAN MICROELECTRONICS TECH INST
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