Fan-out type wafer level encapsulation structure and preparation method thereof

A wafer-level packaging, fan-out technology, used in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of packaging structure interface delamination risk, high difficulty and cost, and impact on reliability, etc. Achieve the effect of avoiding the risk of interface delamination, improving packaging efficiency and improving reliability

Pending Publication Date: 2017-05-17
SJ SEMICON JIANGYIN CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a fan-out wafer level packaging structure and its preparation method, which is used to solve the

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  • Fan-out type wafer level encapsulation structure and preparation method thereof
  • Fan-out type wafer level encapsulation structure and preparation method thereof
  • Fan-out type wafer level encapsulation structure and preparation method thereof

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Example Embodiment

[0097] The following describes the implementation of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0098] See figure 2 The first embodiment of the present invention relates to a fan-out wafer-level packaging structure. It should be noted that the illustrations provided in this embodiment mode only illustrate the basic idea of ​​the present invention in a schematic manner. The figures only show the components related to the present invention instead of the number, shape, and shape of the components in actual implementation. For size drawin...

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Abstract

The invention provides a fan-out type wafer level encapsulation structure and a preparation method thereof. The encapsulation structure comprises at least a rewiring layer; at least one flip chip with a bump protection structure embedded in the upper surface of the rewiring layer and at least two first bumps formed on the upper surface of the rewiring layer; a plastic encapsulation layer of the flip chip formed on the upper surface of the rewiring layer and filled with the bump protection structure, a joint gap between the rewiring layers and the flip chip with the bump protection structure and part of the first bumps; and a second bump formed on the lower surface of the rewiring layer. The plastic encapsulation layer provides a seamless bonding and an excellent connection structure for the flip chips and the rewiring layers, the risk of boundary separations is avoided, and the reliability of the plastic encapsulation structure is increased; meanwhile the flip chips with the bump protection structures are adopted so that bumps are effectively protected and fixedly interconnected, and the interconnected bumps are prevented from losing efficacy.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a fan-out wafer-level packaging structure and a preparation method thereof. Background technique [0002] Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing the minimum feature size. Currently, advanced packaging methods include: Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package (FOWLP), Flip Chip, Package on Package (Package on Package, POP) and so on. [0003] Fan-out wafer-level packaging is an embedded chip packaging method for wafer-level processing. It is currently one of the advanced packaging methods with more input / output ports (I / O) and better integration flexibility. Compared with conventional wafer-level packaging, fan-out wafe...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/488H01L21/56H01L21/60
CPCH01L21/563H01L21/568H01L23/3128H01L24/11H01L24/14H01L2224/11002H01L2224/11019H01L2224/1191H01L2224/81005H01L2924/15192H01L2924/18161
Inventor 吴政达林正忠
Owner SJ SEMICON JIANGYIN CORP
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