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Low-power and high-linearity switching method for successive approximation register (SAR) ADC capacitor array

A capacitor array, successive approximation technology, applied in the field of integrated circuits, can solve the problems of power consumption and speed optimization, large scale of capacitor array, disadvantage, etc., to achieve the effect of improving flexibility, reducing chip area and saving cost

Active Publication Date: 2017-05-17
XIAN UNIV OF POSTS & TELECOMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional charge redistribution SAR ADC capacitor array switching method corresponds to a large capacitor array, which is not conducive to the optimization of area, matching performance, power consumption and speed

Method used

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  • Low-power and high-linearity switching method for successive approximation register (SAR) ADC capacitor array
  • Low-power and high-linearity switching method for successive approximation register (SAR) ADC capacitor array
  • Low-power and high-linearity switching method for successive approximation register (SAR) ADC capacitor array

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Embodiment Construction

[0019] In order to express the purpose, technical solution and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings. Here, the embodiments and descriptions of the present invention are only for explaining the present invention, not as limiting the present invention.

[0020] (1) Description of technical terms involved in the present invention

[0021] SAR: Successive Approximation Register, successive approximation register;

[0022] ADC: Analog-to-Digital Converter, analog / digital converter;

[0023] LSB: Least-Significant-Bit, the least significant bit;

[0024] (2) working principle of the present invention

[0025] refer to figure 1 and figure 2 , for the capacitor array switching method disclosed in the present invention, after the sampling is finished, the comparator compares V ip and V in The size of the output directly produces the highest bit B N-1 , thi...

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Abstract

The invention discloses a low-power and high-linearity switching method for successive approximation register (SAR) ADC capacitor array, which belongs to the technical field of the super low-power design of successive approximation ADC. The method belongs to a switching method of three baselines (Vref, Vcm=Vref / 2 and Gnd=0) based on top-plate sampling; therefore, the scale of the corresponding capacitor array can be reduced by 75% from that of the traditional structure. According to the method, switch control time sequence is initialized; a logic switching mode is utilized featuring the reasonable combination of the down switching and the up switching of capacitors. Under the condition that parasitic capacitance is not considered, the power consumption incurred from capacitor array conversion is only 1.2% of that of the traditional structure; when the parasitic capacitance at the top plate is 10% per unit of capacitor and the parasitic capacitance at the bottom plate is 15% per unit of capacitor, the power consumption incurred from capacitor array conversion is only 1.3% of that of the traditional structure. In addition, compared with the available switching schemes, the method could realize the significant improvement in the linearity of a D / A conversion structure inside an SAR ADC.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to successive approximation ADC capacitor arrays, in particular to a low-power-consumption and high-linearity switching method for successive approximation ADC capacitor arrays. Background technique [0002] With the advantages of low power consumption, the charge redistribution successive approximation (SAR) ADC with capacitor array as the main structure has been widely used in implanted bioelectronics systems such as EEG and ECOG, especially those based on upper plate sampling. Triple reference (V ref , V cm =V ref / 2 and Gnd=0) capacitor array switching method, the number of unit capacitors in the corresponding capacitor array is only 1 / 4 of the traditional structure, which is very suitable for application in implantable biomedical electronic systems. In the charge redistribution SAR ADC, the switching mode of the capacitor array not only affects the power consumptio...

Claims

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Application Information

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IPC IPC(8): H03M1/00H03M1/12H03M1/40
CPCH03M1/002H03M1/1205H03M1/1245H03M1/403
Inventor 佟星元
Owner XIAN UNIV OF POSTS & TELECOMM
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