Shift register and grid electrode driving circuit

Abstract

The invention relates to the field of display, and provides a shift register. The shift register comprises a first input module, a second input module, a pull-up module, an output module, a first capacitor, a second capacitor and a third capacitor, wherein the first input module is electrically connected with a signal input end and a first signal end, and transmits a signal input by the first signal end to a third node by control of the signal input end; the second input module is electrically connected with the signal input end, the first signal end, a second signal end and a first clock signal end, and transmits a signal input by the signal input end to a first node; the pull-up module is electrically connected with the first clock signal end, the second signal end and a second clock signal end, and transmits a signal input by the second signal end to a second node; the output module is electrically connected with the first signal end, the second clock signal input end and an output end, and transmits the signal input by the first signal end or a signal input by the second clock signal end to the output end.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register and a gate drive circuit. Background technique [0002] With the continuous development of display screens, consumers have higher and higher requirements for the stability of display screens. The stability of the display screen is largely reflected in the gate drive circuit and the shift registers that make up the gate drive circuit. [0003] At present, the shift register mostly adopts a 5T2C structure (that is, includes 5 TFT thin film transistor switches and 2 capacitors). Such as figure 1 as shown, figure 1 In a shift register provided in the prior art, the first switch M1 to the fifth switch M5 are all P-type thin film transistors. When the output terminal OUT outputs a low-level signal, the third switch M3 is turned on due to the low-level signal output from the output terminal OUT, and at this time, the high-level signal output from the high-level sig...

AI Technical Summary

Problems solved by technology

If the first node N1 is always in the high level state, the output terminal OUT will output abnormally, which will cause the competition risk of the circuit and cause the shift register to be unstable.

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