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Bare chip and printed circuit board connection and protection structure and manufacturing method thereof

A technology for printed circuit boards and protective structures, which is applied in the fields of circuits, semiconductor/solid-state device manufacturing, and electrical components. It can solve the high requirements for PCB board processing accuracy and the technical level of bonding operators, and the development cycle of fixtures cannot meet the needs of chips. Test timeliness requirements, difficulty in effective connection, etc., to achieve the effect of good engineering application implementability, guaranteed reuse, and avoiding complicated steps and costs

Active Publication Date: 2019-02-22
DEEPBLUE TECH (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Wafer-level testing can test bare chips through wafer probes and special test benches, but it can only complete relatively simple test tasks, and has more limitations in testing the actual functions of chips; some foreign companies have launched KGD ( Known Good Die) bare chip products, using special fixtures to test the bare chip, the special customization of the fixture and the development cycle still cannot meet the timeliness requirements of chip testing; at present, it is more common to fix the bare chip on the PCB board, Use a bonding machine to connect the chip pins and PCB board pads, and then use special glue to cover and protect the entire structure, so that the chip can be fully functionally tested in the laboratory environment
However, once the glue is cured, it is difficult to remove from the bare core, and the maintainability is not good, and the process of covering the bare chip with the glue may cause contact and connection between the bonding wires, resulting in poor reliability.
With the increasing complexity of chips and hundreds of functional pins, it is necessary to process the same number of bonding pads on the PCB as bonding points. Due to the length requirements of bonding wires, metal bonding soldering The disk area and spacing are limited, and it is very easy to cause contact connection between the bonding wires during bonding. The requirements for the processing accuracy of the PCB board and the technical level of the bonding operator are high, and multi-pin bare chips can be realized under ordinary laboratory conditions. It is more difficult to effectively connect with the PCB board; and the larger the area of ​​the bare chip, the more conductive glue is required for bonding on the PCB board. When the bare chip is pressed on the PCB board, the conductive glue will be on the bare chip. The overflow on the side is very easy to adhere to the metal pad of the bare chip, forming a short circuit between the metal pads, causing the bare chip to be scrapped

Method used

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  • Bare chip and printed circuit board connection and protection structure and manufacturing method thereof
  • Bare chip and printed circuit board connection and protection structure and manufacturing method thereof
  • Bare chip and printed circuit board connection and protection structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0046] See figure 1 , figure 1 A structural schematic diagram of a connection and protection structure between a bare chip and a printed circuit board provided for an embodiment of the present invention, wherein the structure 100 includes: a main PCB board 101, a secondary PCB board 103, a bare chip 105, and a first pad 107 , the second pad 109, the bonding wire 111, the metal pin 113, the airtight protective cover 115 and the gasket 119;

[0047] Wherein, the pad 119 is bonded on the main PCB 101, and the bare chip 105 is bonded on the pad 119; the first pad 107 surrounds the bare chip 105 and Set on the main PCB 101 and connected to the metal PAD of the bare chip 105 through the bonding wire 111; the secondary PCB 103 is located on the periphery of the first pad 107 and bonded to the main PCB 101 and realize the electrical connection with the main PCB board 101 through the metal pin 113; The metal PAD connection of the chip 105; the airtight protective cover 115 is bonded...

Embodiment 2

[0065] See Figure 5 , Figure 5 It is a schematic flowchart of a method for manufacturing a connection between a bare chip and a printed circuit board and a protective structure provided by an embodiment of the present invention. Wherein, the manufacturing method includes:

[0066] Making the main PCB board 101, and making the first pad 107 on the surface of the main PCB board 101;

[0067] Adhesive pads 119 at specified positions on the surface of the main PCB 101 and bond bare chips 105 on the surface of the pads 119;

[0068] Bonding both ends of the bonding wire 111 to the metal PAD of the bare chip 105 and the first pad 107 using a bonding process;

[0069] Make the secondary PCB board 103 and make the second pad 109 on the surface of the secondary PCB board 103;

[0070] Bonding the secondary PCB board 103 on the main PCB board 101;

[0071] The two ends of the bonding wire 111 are bonded to the metal PAD of the bare chip 105 and the second pad 109 using a bonding ...

Embodiment 3

[0077] See Figure 7 , Figure 7 It is a schematic flowchart of another manufacturing method for connecting a bare chip to a printed circuit board and a protective structure provided by an embodiment of the present invention. Wherein, the manufacturing method includes:

[0078] Select the main PCB board 101, make the first boundary line 201 of the bonding gasket 119 on the surface of the main PCB board 101, the second boundary line 203 of the bonding sub-PCB board 103 and the third bonding line of the airtight protective cover 115. Boundary line 205; and on the surface of the main PCB 101 along the periphery of the first boundary line 201, make the first pads 107 in a staggered arrangement;

[0079] The gasket 119 is bonded on the surface of the main PCB 101 along the first boundary line 201 and the bare chip 105 is bonded on the surface of the gasket 119, and the bare chip 119 is connected by a bonding wire 111. The metal PAD of the chip 105 and the first pad 107;

[0080...

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PUM

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Abstract

The present invention discloses a bare chip and printed circuit board connection and protection structure and a manufacturing method thereof. The structure 100 comprises: a main PCB 101 and a secondary PCB 103, a bare chip 105, a bonding pad 107, a bonding pad 109, a bonding wire 111, a metal contact pin 113, an airtight protective cover 115 and a gasket 119. The gasket 119 is bonded on the main PCB 101, and the bare chip 105 is bonded on the gasket 119; the bonding pad 107 encircles the bare chip 105, is arranged on the main PCB 101 and is connected with the metal PAD of the bare chip 105 through the bonding wire 111; the secondary PCB 103 is located at the periphery of the bonding pad 107, bonded on the main PCB 101 and is electrically connected with the main PCB 101 through the metal contact pin 113; the bonding pad 109 is made on the secondary PCB 103 and is in metal PAD connection with the bare chip 105 through the bonding wire 111; and the airtight protective cover 115 is bonded on the main PCB 101. The connection structure is high-low high-order shaped to improve the density of the bonding wire on the unit area and ensure that the metal PAD is prevented from pollution when the chip is bonded so as to prevent the bare chip and the bonding wire form oxidation in the air.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit testing, and relates to a connection and protection structure between a bare chip and a printed circuit board and a manufacturing method thereof. Background technique [0002] After the chip tape-out is completed, the bare chip is generally packaged in plastic or ceramic materials to provide environmental protection, and then various functional tests can be performed. The packaging cycle takes up valuable testing time and slows down the pace of product marketization. Therefore, testing bare chips has become a hot spot in international research. [0003] Wafer-level testing can test bare chips through wafer probes and special test benches, but it can only complete relatively simple test tasks, and has more limitations in testing the actual functions of chips; some foreign companies have launched KGD ( Known Good Die) bare chip products, using special fixtures to test the b...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/16H01L21/60
CPCH01L23/16H01L24/32H01L24/48H01L24/83H01L24/85H01L2224/32227H01L2224/48229H01L2224/83051H01L2224/85
Inventor 王起
Owner DEEPBLUE TECH (SHANGHAI) CO LTD