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Thin film transistor and its preparation method, array substrate and electronic equipment

A technology for thin film transistors and source-drain electrodes is applied in the field of preparing the thin film transistors, and can solve the problems of the thin film transistors to be improved, the problem of ohmic contact damage to the active layer, and the complex process.

Active Publication Date: 2020-04-17
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Traditional top-gate LTPS TFT usually needs to prepare LS (light shielding layer), source / drain doping (S / D doping), lightly doped drain region (Ldd doping) and other processes, the process is complicated and the cost is high
Bottom-gate LTPS TFT does not require LS layer and doping process, but it is difficult to solve the damage to the active layer (active layer) and the ohmic contact problem of the back channel etching at the same time
[0004] Therefore, the current thin film transistor technology still needs to be improved

Method used

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  • Thin film transistor and its preparation method, array substrate and electronic equipment
  • Thin film transistor and its preparation method, array substrate and electronic equipment
  • Thin film transistor and its preparation method, array substrate and electronic equipment

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Embodiment Construction

[0024] Embodiments of the present invention are described in detail below. The embodiments described below are exemplary only for explaining the present invention and should not be construed as limiting the present invention. If no specific technique or condition is indicated in the examples, it shall be carried out according to the technique or condition described in the literature in this field or according to the product specification. The reagents or instruments used were not indicated by the manufacturer, and they were all commercially available conventional products.

[0025] In one aspect of the invention, the invention provides a thin film transistor. According to an embodiment of the present invention, refer to figure 1 , the thin film transistor comprises: a gate 10; a gate insulating layer 20; an active layer 30; a source-drain electrode 40, wherein the material of the active layer is polysilicon, and the source-drain electrode 40 is close to the gate 10 A protec...

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Abstract

The invention provides a thin film transistor and its preparation method, an array substrate and an electronic device. The thin film transistor comprises: a gate; a gate insulating layer; an active layer; a source-drain electrode, wherein the source-drain electrode is close to the gate The surface is provided with a protective structure. The inventors have found that by providing a protective structure on the surface of the source and drain electrodes close to the gate, damage to the active layer during the etching process can be avoided, and the channel region of the active layer will not be eroded, thereby greatly improving the performance of the active layer. The performance of thin film transistors.

Description

technical field [0001] The present invention relates to the field of display technology, and specifically relates to a thin film transistor, an array substrate containing the thin film transistor, an electronic device containing the array substrate, and a method for preparing the thin film transistor. Background technique [0002] With the development of liquid crystal display technology, the requirements for electron mobility of the TFT (thin film transistor) semiconductor layer are getting higher and higher, and low temperature polysilicon technology (LTPS) has emerged as the times require. LTPS display technology significantly improves pixel writing speed, so that thinner line width, smaller TFT switch and higher aperture ratio can be set. [0003] The traditional top-gate LTPS TFT usually needs to prepare LS (light shielding layer), source / drain doping (S / D doping), lightly doped drain region (Ldd doping) and other processes, which are complicated and costly. Bottom-gat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/786H01L29/06H01L27/12H01L21/77H01L21/336
CPCH01L27/12H01L29/06H01L29/66227H01L29/786H01L21/77H01L29/78618H01L21/47635H01L27/1225H01L29/267H01L29/45H01L29/66765H01L29/66969H01L29/78609H01L29/7869
Inventor 何晓龙李东升班圣光黄睿米东灿
Owner BOE TECH GRP CO LTD
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