A Synchronous Clock Keeping System and Method with Learning Function
A technology for synchronizing clocks and learning functions, applied in time division multiplexing systems, synchronizing devices, transmission systems, etc., can solve the problem that crystal oscillators cannot be effective and low-cost, and achieves a stable performance that is not easy to interfere, improves synchronization retention performance, and reduces crystal oscillator characteristics. effect of influence
Active Publication Date: 2018-10-09
HEBEI FAREAST COMM SYST ENG
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Problems solved by technology
Through the continuous learning of the clock characteristics, the clock frequency change curve is predicted, and when the synchronization source information is lost, the predicted value is output, which improves the synchronization performance and solves the problem that the existing crystal oscillator cannot meet the synchronization performance requirements effectively and at low cost.
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[0044] The present invention will be described in more detail below with examples in conjunction with the accompanying drawings.
[0045] figure 1It is a structural block diagram of the present invention, a synchronous clock keeping system with a learning function, comprising: an antenna feeder unit 1, a synchronous timing receiving unit 2, a digital phase-locked loop unit 3, a system clock generating unit 5, and a temperature measuring unit 6, which The feature is that it also includes a feature learning prediction unit 4;
[0046] The antenna feed unit 1 is used to receive the timing signal from the satellite, and send the timing signal to the synchronous timing receiving unit 2. Generally, the GPS active antenna is selected, and the power supply voltage is usually 5V or 3.3V; the synchronous timing receiving unit 2 is used to transmit the timing signal Analyze, get the second pulse signal, send the second pulse signal to the digital phase-locked loop unit 3, often choose G...
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The invention discloses a synchronized clock maintenance system and method having a learning function, belonging to the field of clock synchronization. The system and method aim to solve the problem that a synchronization system is difficult to maintain the high synchronization performance within the lost time period of a synchronous source. According to the invention, a feedback unit receives the satellite signal, a synchronous timing reception unit acquires the second pulse signal, the constant temperature crystal oscillator is used as the reference to generate the system clock of a digital phase-locked loop, the digital phase-locked loop generates the synchronized clock signal, the frequency tuning word is sent to a characteristic learning prediction unit which makes a prediction according to the characteristic equation of the tuning word, and when the synchronous source is lost, the digital phase-locked loop generates the synchronized clock signal according to the prediction equation. The system and method are mainly used in the system having high synchronization performance requirement and being incapable of using an atomic clock, and can obviously improve the synchronization performance after the synchronous source signal is lost.
Description
technical field [0001] The invention relates to the field of clock synchronization, in particular to a system and method for maintaining synchronization performance when a synchronization source signal is lost. Background technique [0002] In recent years, clock synchronization technology has made great progress, and it also plays an increasingly important role in science and technology, national defense, and social security. The clock synchronization technology mainly involves two aspects of technology, one is the clock source technology, and the other is the phase-locked loop technology. With the improvement of application requirements and technical process, clock source technology and phase-locked loop technology have also been developed rapidly. [0003] The synchronous clock hold function is an important function of the clock synchronization technology. The synchronous clock hold performance is mainly limited by the stability of the crystal oscillator. When the input ...
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IPC IPC(8): H04J3/06H04L7/033
CPCH04J3/0638H04L7/033
Inventor 彭磊磊康志杰张松轶王伟孙敬伟高晓伟孙剑宇田双彪李万松杜义浩
Owner HEBEI FAREAST COMM SYST ENG