Method for improving chip simultaneous testing number

Abstract

The invention discloses a method for improving a chip simultaneous testing number. The method comprises the following steps that: (1) placing a BIST (Built-in Self Test) circuit in a scribe line gap between chips; (2) connecting the BIST circuit with peripheral chips through a data bus; (3) sending a control signal to the BIST circuit by automatic testing equipment, selecting a plurality of connected tested chips, and carrying out a multi-chip test; (4) carrying out feedback on a test result and the state of a data register to the automatic testing equipment by the BIST circuit, determining the PASS/FAIL situation of each tested chip and failure modes and positions in the chips by the automatic testing equipment according to the test result and the data register so as to realize the simultaneous testing of multiple chips; and (5) after testing is finished, when a silicon wafer is cut and picked up, removing the BIST circuit from the scribe line. By use of the method for improving the chip simultaneous testing number, the simultaneous testing of multiple chips can be realized, and additional chip areas are not increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for improving the number of simultaneous measurements of chips. Background technique [0002] With the improvement of circuit integration and circuit complexity, the test cost of automatic test equipment is getting higher and higher. In addition, due to the constraints of the test environment of the automatic test equipment, it will be more and more difficult to realize the high-speed mixed-signal automatic test equipment, and it is impossible for a large number of signals in the chip to lead out to the automatic test equipment for testing through the PAD. [0003] BIST circuit can be used to provide self-test function, so as to reduce the dependence of chip test on automatic test equipment, which has the advantages of reducing test cost, improving error coverage, shortening test time, and independent testing. [0004] The currently known BIST circuit is built on...

AI Technical Summary

Problems solved by technology

[0004] The currently known BIST circuit is built on the chip during the test process, and the BIST circuit part is removed after the test is completed, as shown in the attached figure 1 As shown; this BIST circuit has the following defects: (1) BIST circuit needs to take extra chip area, thereby causes the increase of chip area, causes the waste of production cost and process; (2) builds up on the BIST circuit on the chip, only Can be tested for the corresponding chip, but cannot be connected with other chips, so it is impossible to test multiple chips at the same time, and it cannot effectively save test time

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