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Test tray for test handler and interface board for tester

A technology for testing sorting machines and test trays, which is applied in the direction of single semiconductor device testing, electrical measuring instrument components, sorting, etc., and can solve the problem of removing calibration pins from calibration holes, and the electrical connection between semiconductor components and test sockets. Achievement, restriction and other issues, to achieve the effect of minimizing assembly tolerances

Active Publication Date: 2017-08-01
TECHWING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If manufacturing tolerances are not considered, due to errors generated when the calibration pins are inserted into the calibration holes, the manufacturing tolerances may cause operational failure or damage to the insert, and therefore, the electrical connection between the semiconductor element and the test socket cannot be properly achieved.
In addition, if the correction pin is inserted into the correction hole in a forced fit, it may be difficult to remove the correction pin from the correction hole afterwards.
[0009] Therefore, prior art techniques have limitations in accurately correcting the position of the insert when microspacing between micronized terminals and terminals of reduced size

Method used

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  • Test tray for test handler and interface board for tester
  • Test tray for test handler and interface board for tester
  • Test tray for test handler and interface board for tester

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0061] 1. Test tray for testing sorting machine

[0062] figure 1 is a plan view of a test tray 100 (hereinafter referred to as "test tray") for testing a sorter according to a first embodiment of the present invention.

[0063] The test tray 100 according to the first embodiment includes a plurality of inserts 110 and a mounting frame 120 .

[0064] Each of the inserts 110 includes a body 111 , a support member 112 and a retainer 113 .

[0065] The body 111 has a placement space SS on which a semiconductor element may be placed. In addition, the body 111 has two first calibration holes CH1 and four second calibration holes CH2.

[0066] The first correction hole CH1 is formed to have an inner diameter in consideration of manufacturing tolerances, which has been described in [Prior Art]. The first calibration hole CH1 is used to firstly correct the position of the insert 110 .

[0067] The second correction hole CH2 is formed to secondly and more accurately correct the ...

Embodiment 2

[0099] Figure 8 is a plan view of a test tray 700 for a test sorter (hereinafter referred to as "test tray") according to a second embodiment of the present invention.

[0100] In this embodiment, the test tray 700 includes a plurality of inserts 710 and a mounting frame 720 .

[0101] The insert 710 includes a body 711 , a support member 712 and a holder 713 . Here, descriptions of the support member 712 and the holder 713 will be omitted since they are the same components as those of the first embodiment.

[0102] The body 711 has a placement space SS on which a semiconductor element is placed. In addition, the body 711 has a correction hole CH and a cutout hole IH.

[0103] The position of the insert 710 is corrected because a correction pin of the interface board (the same as the first correction pin in the first embodiment) is inserted into the correction hole CH. hereby, if Figure 9 As shown in , the wall surface W of the correction hole CH has a cutout portion IP...

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PUM

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Abstract

The present invention relates to a test tray for a test handler and an interface board for a tester. According to the present invention, a secondary calibration hole is additionally formed in an insert of a test tray, and a secondary calibration pin is provided in a socket guider of an interface board. In addition, an alignment hole is additionally formed in a test socket of an interface board, and an alignment pin is provided in the interface board. Accordingly, the position of an insert can be calibrated in divided steps. Furthermore, a wall surface forming a calibration hole of an insert body is cut, and an incision hole is formed around the calibration hole. According to the present invention, the position of an insert is calibrated sequentially in divided steps, thereby enabling very accurate calibration of the position of an insert. In addition, a calibration pin is prevented from being fitted into a calibration hole, thereby enabling formation of a smaller calibration hole and finer calibration of the position of an insert.

Description

technical field [0001] The present invention relates to a test tray and an interface board for a test sorter. Semiconductor components are loaded on the test sorter, and the interface board is connected to the semiconductor component in the test machine. Background technique [0002] The test handler moves the semiconductor components manufactured through the specified process from the customer tray to the test tray; at the same time supports the testing of the semiconductor components loaded on the test tray by the tester; and then moves the semiconductor components from the test tray to the customer Trays, while sorting semiconductor components by grade based on test results. This test sorter has been revealed through various public documents. [0003] The test tray has a structure in which inserts are mounted on the mounting frame, the inserts have placement spaces, and semiconductor elements are inserted and placed in each of the inserts. [0004] Each of the inserts h...

Claims

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Application Information

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IPC IPC(8): B07C5/02B07C5/344G01R31/26G01R1/04
CPCG01R1/0408G01R1/0416G01R31/26B07C5/02B07C5/344
Inventor 罗闰成黄正佑崔僖峻
Owner TECHWING CO LTD
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