Implementation method of OpenPOWER CPU boot based on CPLD

Abstract

The invention discloses an implementation method of OpenPOWER CPU boot based on a CPLD, including the CPLD communication connection between a BMC and POWER CPU. The method is characterized by comprising the following steps: the BMC sends a boot command to the CPLD; the CPLD receives the boot command of the BMC, converts the boot command into an FSI protocol, and sends the FSI protocol to the POWER CPU, and the POWER CPU returns an execution result to the CPLD through the FSI protocol; and the CPLD receives the result returned by the POWER CPU, and returns the return result to the BMC for further processing. The implementation method disclosed by the invention adopts the CPLD that meets the requirements of the FSI protocol, includes a handshake process, ensures that the operating frequency can be up to 166MHz, is short in boot time, low in noise and high in signal quality, and ensures that the stability can be enhanced and the risks and hidden dangers of unreliable communication can be overcome.

Description

technical field [0001] The invention relates to the technical field of OpenPOWER CPU boot, in particular to a method for realizing OpenPOWER CPU boot based on CPLD. Background technique [0002] At present, the OpenPOWER CPU boot technology uses the FSI (Field Replaceable Unit ServiceInterface) protocol for communication. However, only IBM's FSP (Flexible Service Processor) implements FSIboot communication, and the limitation is that FSP is not public. The third-party baseboard management controller BMC simulates FSI through the general-purpose input and output pins GPIO, and sends the boot command sequence. The GPIO rate is generally 2MHz, 10MHz, and 50MHz. The higher the GPIO rate, the greater the noise and the worse the signal quality. On the one hand, the GPIO rate On the other hand, if the return result is received through GPIO, the GPIO output needs to be switched to the input, which increases the delay. The FSI operating frequency can reach up to 166MHz, far exceedi...

AI Technical Summary

Problems solved by technology

However, only IBM's FSP (Flexible Service Processor) implements FSIboot communication, and the limitation is that FSP is not public

The third-party baseboard management controller BMC simulates the FSI through the general-purpose input and output pin GPIO, and sends the boot command sequence. The GPIO rate is generally 2MHz, 10MHz, and 50MHz. On the other hand, if the return result is received through GPIO, the GPIO output needs to be switched to input, which increases the delay

Third-party BMC simulates many FSIs through GPIO, and the limitation is that GPIO cannot receive command return results, and the simulation lacks a handshake process. There are risks and hidden dangers of unreliable communication, which may cause loss of return results. Once the execution fails, BMC cannot obtain the system. status; on the other hand, the speed of GPIO is slow, which prolongs the boot time to a certain extent

In order to give full play to the high-frequency advantages of CPLD and FSI that meet the requirements of the FSI protocol, increase the handshake process, overcome the risks and hidden dangers of unreliable communication such as large noise, poor signal quality, and loss of returned results, and shorten the boot time, it is necessary to propose a The new OpenPOWER CPU boot implementation method solves the above problems

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