Method for analyzing interconnect process variation

A technology of process change and process, which is applied in the field of analyzing interconnection process changes, and can solve problems affecting yield and so on

Inactive Publication Date: 2017-08-11
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Process variations and parasitic RC elements can negatively affect yield, performance and reliability of resulting IC chips

Method used

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  • Method for analyzing interconnect process variation
  • Method for analyzing interconnect process variation
  • Method for analyzing interconnect process variation

Examples

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Embodiment Construction

[0013] The invention provides many different embodiments or examples for implementing the different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature. Embodiments are formed such that the first feature may not be in direct contact with the second feature. Additionally, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various em...

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PUM

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Abstract

The invention provides a method for analyzing interconnect process variation. A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Description

technical field [0001] Embodiments of the present invention relate to a method for analyzing changes in an interconnection process. Background technique [0002] During mass production of integrated circuits (ICs), process variations in the semiconductor manufacturing process can affect the operational performance of the resulting IC chips. Additionally, as semiconductor fabrication processes move toward smaller and smaller feature sizes (e.g., 28 nanometers and below), parasitic resistance-capacitance (RC) elements in the IC's interconnect structure have an increasing effect on the operation of the resulting IC chip . Process variations and parasitic RC elements can negatively affect yield, as well as performance and reliability of the resulting IC chips. IC chip designers use computer simulations to account for process variations and process-induced parasitic RC elements. Contents of the invention [0003] The present invention provides methods for analyzing interconn...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/398G06F30/394G06F2119/18G06F30/3312G01R31/2856G01R31/28G06F30/00G06F30/367
Inventor 刘得佑萧铮陈家逸黄文成苏哿暐苏哿颖喻秉鸿
Owner TAIWAN SEMICON MFG CO LTD
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