Formation method of transistor

Abstract

The invention discloses a formation method of a transistor. The formation method comprises the following steps: forming a substrate, wherein a first well region and a second well region which are adjacent are formed in the substrate; forming an isolation structure in the second well region, wherein the top surface of the isolation structure is lower than the top surface of the first well region and the top surface of the second well region; forming a pseudo grid structure on the substrate; forming a source region or a drain region respectively in second regions of the first well region and the second well region in which the pseudo grid structure is exposed; forming a dielectric layer; forming an opening in the dielectric layer; forming grid dielectric layers on the bottom and the side wall of the opening; forming work function layers on the dielectric layers; carrying out ion injection treatment so as to adjust work functions of the work function layers; and forming grid electrodes. After the step of forming the work function layers and before the step of forming the grid electrodes, the ion injection treatment is carried out on the work function layers so as to adjust the work functions of the work function layers, so that the problem that the threshold voltage distribution of the transistor is non-uniform is solved, the punch-through of the grid dielectric layers is reduced, and the performance of the formed transistor is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] Laterally Diffused Metal Oxide Semiconductor (LDMOS) is a commonly used high-voltage device. [0003] LDMOS is widely adopted due to its easier compatibility with CMOS processes. LDMOS is a power device with a double-diffusion structure. Two implants are performed in the same source region or drain region, one with a higher concentration of arsenic ions and the other with a lower concentration of boron ions. After implantation, a high-temperature push process is performed. Since boron ions diffuse faster than arsenic ions, boron ions will diffuse farther below the gate boundary along the lateral direction, thereby forming a channel with a concentration gradient. The length of the LDMOS channel is determined by the difference between the two lateral diffusion distances. [0004] In order to improve the w...

AI Technical Summary

Problems solved by technology

However, in the prior art, LDMOS whose gate structure extends to the drift region often has the problem that the gate dielectric layer is easily broken down, which affects the withstand voltage performance of LDMOS.

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