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Grid and method of making the same

A manufacturing method and gate technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as uneven distribution of threshold voltage, and achieve the effect of improving uneven distribution of threshold voltage and increasing mobility

Active Publication Date: 2018-07-20
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of this application is to provide a gate and its manufacturing method to improve the problem of uneven threshold voltage distribution in the existing gate

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] This embodiment provides a method for fabricating a grid, including the following steps:

[0045] Formation of HfO by Atomic Layer Deposition Process 2 Gate dielectric layer, the process conditions are: with HfCl 4 and H 2 O is the reactive gas, N 2 as the carrier, where HfCl 4 The flow rate is 100sccm, H 2 The flow rate of O is 100 sccm, N 2 The flow rate is 2000 sccm, the deposition pressure in the chamber is 1.5 Torr, and the deposition temperature is 400°C.

[0046] using atomic layer deposition on HfO 2 An amorphous TiAlN gate material layer is formed on the gate dielectric layer, and the process conditions are as follows: TiCl4, trimethylaluminum and NH 3 is the reactive gas, where TiCl 4 The flow rate is 30sccm, the flow rate of trimethylaluminum is 20sccm, NH 3 The flow rate is 100 sccm, the deposition pressure in the chamber is 1 Torr, and the deposition temperature is 350°C. In the formed amorphous TiAlN, the content of N atoms (the smallest atomic r...

Embodiment 2

[0048] This embodiment provides a method for fabricating a grid, including the following steps:

[0049] Formation of HfO by Atomic Layer Deposition 2 Gate dielectric layer, the process conditions are: with HfCl 4 and H 2 O is the reactive gas, N 2 as the carrier, where HfCl 4 The flow rate is 100sccm, H 2 The flow rate of O is 100 sccm, N 2 The flow rate is 2000 sccm, the deposition pressure in the chamber is 1.5 Torr, and the deposition temperature is 400°C.

[0050] Atomic layer deposition on HfO 2 An amorphous TiPC gate material layer is formed on the gate dielectric layer, and the process conditions are as follows: TiCl 4 、PH 3 and CH 4 For the reaction gas, Ar is the carrier, wherein the flow of TiCl4 is 5 sccm, PH 3 The flow rate is 100sccm, CH 4 The flow rate of Ar is 10 sccm, the flow rate of Ar is 1000 sccm, the deposition pressure in the chamber is 2 Torr, and the deposition temperature is 400° C. In the formed amorphous TiPC, the content of C atoms (the...

Embodiment 3

[0052] This embodiment provides a method for fabricating a grid, including the following steps:

[0053] Formation of HfO by Atomic Layer Deposition 2 Gate dielectric layer, the process conditions are: with HfCl 4 and H 2 O is the reactive gas, N 2 as the carrier, where HfCl 4 The flow rate is 100sccm, H 2 The flow rate of O is 100 sccm, N 2 The flow rate is 2000 sccm, the deposition pressure in the chamber is 5 Torr, and the deposition temperature is 400°C.

[0054] Atomic layer deposition on HfO 2 An amorphous WPC gate material layer is formed on the gate dielectric layer, and the process conditions are as follows: WF 6 、PH 3 and C 3 h 8 As the reaction gas, with Ar as the carrier, where WF 6 The flow rate is 20sccm, PH 3 The flow rate is 65sccm, C 3 h 8 The flow rate of Ar is 40 sccm, the flow rate of Ar is 1500 sccm, the deposition pressure in the chamber is 2 Torr, and the deposition temperature is 350° C. In the formed amorphous WPC, the content of C atoms...

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Abstract

The invention discloses a grid electrode and a manufacturing method therefor. The grid at least comprises an amorphous grid metal layer, wherein the amorphous grid metal layer is an amorphous metal alloy material layer or an amorphous metallic compound material layer. The amorphous metal alloy material layer is formed by an amorphous substance containing at least two types of metal elements. The amorphous metallic compound material layer is formed by an amorphous substance which contains at least one metallic element and at least one non-metallic element selected from IIIA main group, IVA main group, and VA main group. Atoms of the amorphous grid metal layer are distributed irregularly and uniformly, and there is no crystal grain and grain boundary, so the amorphous grid metal layer has few effect of causing recombination of charge carriers, thereby enabling the migration rate of the charge carriers of a grid electrode to be improved. Moreover, the charge carriers can be distributed uniformly, thereby solving a problem that the distribution of the threshold voltage of the grid electrode is not uniform.

Description

technical field [0001] The present application relates to the technical field of manufacturing semiconductor integrated circuits, in particular, to a gate and a manufacturing method thereof. Background technique [0002] As the feature size of semiconductor devices continues to shrink, the size of the gate dielectric layer in transistors has shrunk to a critical limit. For example, when using a 65-nanometer process, the thickness of the gate dielectric layer has been reduced to 1-2 nanometers. If the size of the gate dielectric layer is further reduced, the leakage current and power consumption of the transistor will increase sharply. At present, technicians have begun to develop HKMG (high-k dielectric layer / metal gate) for 32nm and below generations to reduce leakage current and power consumption in transistors. Among them, the high K dielectric layer is mainly HfO 2 , the metal gate is mainly TiN. [0003] However, there are many defects on the grain boundary of the e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/423H01L21/28
CPCH01L21/28008H01L29/4232
Inventor 三重野文健
Owner SEMICON MFG INT (SHANGHAI) CORP
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