Two-stage splitting router applied to hierarchical network on chip and routing algorithm thereof

A router and routing technology, applied in the direction of data exchange network, digital transmission system, electrical components, etc., can solve the problem of increasing data packet delay, achieve the effect of increasing complexity and improving transmission efficiency

Active Publication Date: 2017-08-15
HEFEI UNIV OF TECH +1
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] However, in order to avoid a deadlock situation, the algorithm stipulates that all multicast data packets in an area must enter the area from the upper router, even if a source node perfo

Method used

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  • Two-stage splitting router applied to hierarchical network on chip and routing algorithm thereof
  • Two-stage splitting router applied to hierarchical network on chip and routing algorithm thereof
  • Two-stage splitting router applied to hierarchical network on chip and routing algorithm thereof

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Embodiment Construction

[0050] In this embodiment, the format of the data packet is as shown in Table 1. Each multicast data packet header microchip includes a virtual channel number flag, a microchip type flag, a data packet type flag, a destination node number, a source node number, a data packet current Transmission path, upper layer node number in the area where the destination node is located, upper layer network transmission direction;

[0051] Table 1 Network packet format

[0052]

[0053]

[0054] The hierarchical on-chip network structure adopted is a two-layer on-chip network composed of a 6×6 bottom-level two-dimensional network and a 2×2 upper-layer network, such as figure 1 As shown; the underlying two-dimensional network is divided into four areas; each area contains an intermediate router and several ordinary routers; ordinary routers include five transmission directions; intermediate routers include five transmission directions and one upward transmission direction; the upper l...

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Abstract

The invention discloses a two-stage splitting router applied to a hierarchical network on a chip and a routing algorithm thereof. The two-stage splitting router is characterized in that a decoding module of the router is set into a multicast routing computation module; and the multicast routing computation module comprises a classification decoding unit YM, a unicast data packet routing computation unit SR, a multicast uplink data packet routing computation unit UR, a multicast downlink data packet routing computation unit DR and an output port register unit. Through adoption of the two-stage splitting router, a hybrid multicast routing algorithm can be optimized and improved at a certain degree, and data in multicast data packets are selectively split and transmitted through a two-stage splitting method, so that delay of the multicast data packets is lowered, and meanwhile the congestion state of an upper-layer network is optimized.

Description

technical field [0001] The invention belongs to the communication technical field of integrated circuit on-chip networks, and in particular relates to a two-level split router and routing algorithm applied to hierarchical on-chip networks. Background technique [0002] With the continuous increase of the number of cores on the network on chip, the parallel communication between multiple cores makes the communication relationship of the network on chip quite complicated. The traditional network-on-chip design only considers the unicast communication mode from one source node to one destination node. It has become an increasingly important communication requirement to implement multicast communication from a single source node to multiple destination nodes on a network-on-chip. [0003] Currently, there are many multicast routing algorithms, among which, the hybrid multicast routing algorithm based on hierarchical network structure adopts a two-layer network structure and div...

Claims

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Application Information

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IPC IPC(8): H04L12/715H04L12/761H04L12/801H04L45/16
CPCH04L45/04H04L45/16H04L47/12
Inventor 杜高明张永亮胡巧张多利宋宇鲲王晓蕾
Owner HEFEI UNIV OF TECH
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