A method for arranging semiconductor wafers to improve chip yield

Abstract

The invention discloses an arrangement method for improving chip generation rate of a semiconductor wafer. Blocks for placing chips are arranged in the semiconductor wafer. The arrangement method comprises the following steps of a, placing partial board or total board of PCM parameter testing information into an idle area of the chip board; and b, placing the board of alignment information and partial board, which is not placed into the chip, of the PCM parameter testing information into a scribing trough, thereby reducing the distance between chips in the block. Through the manner of the invention, the arrangement method for improving chip generation rate of the semiconductor wafer is advantageous in that through placing the board blocks for the PCM parameter testing information in partial process manufactures into an actual chip, purposes of reducing the area of the scribing troughs and reducing block area are realized, thereby placing more blocks on the same semiconductor wafer, improving utilization rate of the semiconductor wafer, and realizing cost of a single wafer. The arrangement method improves market competitiveness of a product to a certain extent.

Description

technical field [0001] The invention belongs to the field of semiconductors, and relates to a method for arranging semiconductor wafers, in particular to a method for arranging and processing test layouts used for semiconductor process testing in semiconductor manufacturing. Background technique [0002] With the development of Internet of Things technology, the demand for various sensors is increasing, and many sensors have relatively large areas, such as semiconductor fingerprint sensors, infrared imaging sensors and other signal acquisition, because the acquisition area is directly related to the chip area . [0003] There are two mainstream fingerprint recognition technologies. One is optical fingerprint recognition technology, and the other is semiconductor fingerprint recognition technology. In the past 20 years of fingerprint recognition technology, both technologies have their own applications, but with the rise of mobile devices, the shortcomings of optical method...

AI Technical Summary

Problems solved by technology

The PCM layout area is generally relatively large. When the chip is relatively small, it can be placed in the 80um dicing slot. When the chip is large, since the maximum size of a block (BLOCK) is fixed, the When it is too large, there are not enough scribing slots in the block to place the layout for monitoring PCM parameters and self-alignment, only to expand the scribing slots, which leads to waste of semiconductor wafers

Images