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Via hole etching method for metal self-capacitance touch substrate

A via hole and metal technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., to achieve low over-etching rate, lower resistance value, and improve the effect of poor lap

Inactive Publication Date: 2019-10-22
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of this, in order to solve the problem of etching via holes at different positions of the metal self-capacitance touch substrate, the present invention provides a method for etching via holes of the metal self-capacitive touch substrate, which can, without adding additional processes, Only by changing the mask structure or changing the TFT (Thin Film Field Effect Transistor) structure, the phenomenon of poor touch via hole lapping can be improved

Method used

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  • Via hole etching method for metal self-capacitance touch substrate
  • Via hole etching method for metal self-capacitance touch substrate
  • Via hole etching method for metal self-capacitance touch substrate

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Embodiment 1

[0022] In this embodiment, by changing the structure of the mask plate 16, the phenomenon of poor lapping caused by overcutting of the existing touch vias is improved. 14 is etched and shaped at the same time, so as to avoid the excessive thickness difference of the two types of via holes which will cause poor via hole formation.

[0023] Such as image 3 As shown, the mask 16 adopts a grayscale mask, that is, the pattern on the mask is a grayscale pattern, and the pattern on the mask is set to 100% light-transmitting and partially light-transmitting areas. Specifically, the mask plate 16 is respectively provided with patterns for processing the grid line via hole 13 and the touch control via hole 14, and the pattern for processing the grid line via hole 13 adopts 100% light transmission, and the pattern to be etched The film layers are the gate insulating layer 4, the first insulating layer 7 and the second insulating layer 10, the thickness is greater than 10000A, and the r...

Embodiment 2

[0025] Considering that in the prior art, only a small lateral area of ​​the touch via hole 14 is in electrical contact with ITO (conductive glass), and the resistance of ITO itself is relatively large, which may easily cause excessive contact resistance. In this embodiment, the solution of placing the data line metal buffer layer 15 on the bottom layer of the touch bonding metal 9 is used to improve the phenomenon of poor lapping caused by over-cutting of the existing touch via holes 14 . Such as Figure 4 As shown, a data line metal buffer layer 15 is placed in the first insulating layer 7 below the touch bonding metal 9, the width of the data line metal buffer layer 15 is greater than the width of the touch bonding metal 9, and the data line metal buffer layer 15 The height is smaller than the height of the first insulating layer 7 . Form the photoresist via hole subsequently and carry out dry etching, because the metal etching speed is slow, and the first insulating layer...

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Abstract

The invention discloses a via etching method for a metal self-capacitance touch substrate. On the premise of no additional process, the problem that the touch via of a metal self-capacitance touch substrate is poor in bonding is improved by changing the structure of a mask or changing the structure of a TFT (Thin Film Transistor). One scheme is to change the structure of the mask, namely, photoresist of set thickness is set between a pattern for machining a touch via on the mask and touch bonding metal to make a gate line via and the touch via etched and molded at the same time, and the problem that poor via molding is caused by large thickness difference between the two types of vias is avoided. The other scheme is to put a data line metal buffer layer at the bottom of the touch binding metal to improve the existing phenomenon that touch via over-etching leads to poor bonding.

Description

technical field [0001] The invention relates to a via hole etching method, in particular to a via hole etching method for a metal self-capacitance touch substrate. Background technique [0002] For TFT-LCD (Thin Film Field Effect Transistor LCD) self-capacitance technology products, its structure is based on the existing horizontal electric field driven LCD. A horizontal electric field is formed through the pixel electrode and the uppermost common electrode to drive the liquid crystal in the cell to deflect and realize the display function. With the development of display technology, FIC, that is, built-in touch technology, has become the mainstream. By placing touch metal traces in the TFT and detecting the capacitance change between the traces, the touch function can be realized. [0003] The touch metal wiring is placed in the TFT, and its main function is to detect the capacitance change after the finger touches. After the change is detected, the signal is drawn from th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L21/77
Inventor 喻志农郭建蒋玉蓉薛唯
Owner BEIJING INSTITUTE OF TECHNOLOGYGY