Via hole etching method for metal self-capacitance touch substrate
A via hole and metal technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., to achieve low over-etching rate, lower resistance value, and improve the effect of poor lap
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Embodiment 1
[0022] In this embodiment, by changing the structure of the mask plate 16, the phenomenon of poor lapping caused by overcutting of the existing touch vias is improved. 14 is etched and shaped at the same time, so as to avoid the excessive thickness difference of the two types of via holes which will cause poor via hole formation.
[0023] Such as image 3 As shown, the mask 16 adopts a grayscale mask, that is, the pattern on the mask is a grayscale pattern, and the pattern on the mask is set to 100% light-transmitting and partially light-transmitting areas. Specifically, the mask plate 16 is respectively provided with patterns for processing the grid line via hole 13 and the touch control via hole 14, and the pattern for processing the grid line via hole 13 adopts 100% light transmission, and the pattern to be etched The film layers are the gate insulating layer 4, the first insulating layer 7 and the second insulating layer 10, the thickness is greater than 10000A, and the r...
Embodiment 2
[0025] Considering that in the prior art, only a small lateral area of the touch via hole 14 is in electrical contact with ITO (conductive glass), and the resistance of ITO itself is relatively large, which may easily cause excessive contact resistance. In this embodiment, the solution of placing the data line metal buffer layer 15 on the bottom layer of the touch bonding metal 9 is used to improve the phenomenon of poor lapping caused by over-cutting of the existing touch via holes 14 . Such as Figure 4 As shown, a data line metal buffer layer 15 is placed in the first insulating layer 7 below the touch bonding metal 9, the width of the data line metal buffer layer 15 is greater than the width of the touch bonding metal 9, and the data line metal buffer layer 15 The height is smaller than the height of the first insulating layer 7 . Form the photoresist via hole subsequently and carry out dry etching, because the metal etching speed is slow, and the first insulating layer...
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