High-speed parallel multi-path fractional delay filter implementation method

Abstract

The invention belongs to the technical field of communication, and relates to a high-speed parallel multi-path fractional delay filter implementation technology based on Lagrange interpolation. According to the invention, a fractional delay filter can be applied under the high-speed parallel multi-path condition and meanwhile, by using a Lagrange interpolation algorithm, the process of solving a filter coefficient is simplified. The high-speed parallel multi-path fractional delay filter implementation technology based on Lagrange interpolation, which is disclosed by the invention, is suitable to implement in high-speed platform, such as a FPGA, a DSP and the like, and is convenient for practical application.

Description

technical field [0001] The invention belongs to the technical field of communication, and relates to a high-speed parallel multi-path fractional delay filter realization technology based on Lagrange interpolation. Background technique [0002] The core of broadband beamforming technology is to control the delay of signals in the array to offset the spatial delay of signals from different directions, so that the signals between each array element can be added in phase to obtain beam pointing and directional gain. The high cost, bulky size, high power consumption, and poor stability of analog delay lines are not conducive to practical applications, but delay compensation in the digital domain has the advantages of low cost, high precision, and good stability, and has a good application prospect. In the digital domain, it is very easy to implement a delay that is an integer multiple of the sampling period. For the case of implementing a fractional delay of the sampling period, ...

AI Technical Summary

Problems solved by technology

[0007] Using the traditional Farrow fractional delay filter implementation method, to implement an N-order Farrow fractional delay filter, M×N multipliers are required. When the values ​​​​of N and M are large, the traditional Farrow fractional delay filter structure Very resource consuming, traditional Farrow fractional delay filter structure as attached figure 1 shown

[0008] In addition, the traditional Farrow fractional delay filter has a big defect, that is, it can only be applied to single-channel (single-channel data input, single-channel data output), low data rate application scenarios, if the front-end ADC If the sampling rate reaches 1GHz or more, then according to the traditional Farrow fractional delay filter implementation method, the working clock of the entire system is required to be above 1GHz, which is unrealistic in actual FPGA and DSP applications

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