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Circuit implementation method for avoiding blockage of assembly line

A technology for avoiding blockage and implementing methods, applied in the direction of electrical digital data processing, program control design, instruments, etc., can solve problems such as system design performance impact, chip efficiency reduction, etc., to reduce design optimization pressure, improve design efficiency, and solve efficiency Reduced effect

Inactive Publication Date: 2017-11-24
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

In large-scale data collaborative processing chips, this kind of data correlation often occurs. Using the traditional pipeline structure will reduce the efficiency of the entire chip, which will have a negative impact on the performance of the system design.

Method used

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  • Circuit implementation method for avoiding blockage of assembly line
  • Circuit implementation method for avoiding blockage of assembly line
  • Circuit implementation method for avoiding blockage of assembly line

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Experimental program
Comparison scheme
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Embodiment Construction

[0026] The content of the present invention is described in more detail below:

[0027] like figure 1 As shown, when the D2 data enters the (2) stage pipeline for processing, the result of the Dn-1 data entering the (n) stage processing is required as its input data to participate in the operation. However, at this time, the Dn-1 level data has only reached the (n-1) level pipeline for processing, and it needs to complete the n-level pipeline processing in the next clock cycle, and output the current D2 data in the (2) level pipeline. Therefore, at this time, the pipeline cannot correctly complete the processing that D2 data needs to complete in the (2) stage pipeline.

[0028] According to the traditional solution, to solve the problem from the circuit level, it is necessary to stagnate the D2 and D1 data in the (2) and (1) level pipeline processing, and wait for the Dn-1 data to reach the (n) level pipeline, complete Processing, when the data is output to the (2) stage pip...

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Abstract

The invention provides a circuit implementation method for avoiding blockage of an assembly line, and belongs to the technical field of digital circuit design. The method includes the steps that firstly, D2 data is stored into an available address space X of a Memory A; secondly, the id of each pointer combination is stored in a Memory B, and each id comprises Src.id and addr.x; thirdly, a current dst.id is sent into Dn-1 data to be recorded and stored, wherein the dst.id record is the address position of the id of the current combination in the Memory B. The method can avoid stagnation of the assembly line and improve the execution efficiency of a chip.

Description

technical field [0001] The invention relates to digital circuit design technology, in particular to a circuit realization method for avoiding blockage of pipelines. Background technique [0002] Considering the circuit of the high-speed protocol processing part in the high-speed cooperative protocol processor system, due to the complexity of the protocol processing itself, the circuit scale is large, there are many registers, and it has large dynamic power consumption, high clock frequency, and high The operating frequency of the registers and related combinational logic circuits is extremely high, and there are high design requirements and design difficulties for the power supply and voltage drop changes of the chip circuits. Using the traditional pipeline structure data processing method, each clock The logic complexity of the processing is very high, which poses great challenges to the circuit back-end design. In the traditional pipeline structure processing method, due ...

Claims

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Application Information

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IPC IPC(8): G06F9/38
CPCG06F9/3867
Inventor 赵元
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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