FPGA based redundant double-network-interface configurable Ethernet IP core

An Ethernet, dual network port technology, applied in the field of Ethernet IP core, can solve the problem of inability to realize data transmission, and achieve the effect of low cost

Inactive Publication Date: 2017-11-24
XI'AN INST OF OPTICS & FINE MECHANICS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Based on the current status quo, in some fields where high-definition lossless video transmission requires high stability and reliability,

Method used

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  • FPGA based redundant double-network-interface configurable Ethernet IP core
  • FPGA based redundant double-network-interface configurable Ethernet IP core
  • FPGA based redundant double-network-interface configurable Ethernet IP core

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0030] Such as figure 1 As shown, the FPGA-based redundant dual network port configurable Ethernet IP core in this embodiment is implemented on the StratixII series FPGA architecture system. All circuit boards that meet the following requirements can realize the verification of the IP core.

[0031] 1) There are two PHY chips and two RJ45 network ports on the circuit board;

[0032] 2) There is an FPGA chip that can work and configure normally on the circuit board;

[0033] 3) Two PHY chips are connected to one FPGA chip at the same time;

[0034] 4) The FPGA chip has a custom IO interface.

[0035] FPGA-based redundant dual-network Ethernet IP core, in which the FPGA uses the RGMII interface to communicate with the physical layer PHY chip, and all protocols above the physical layer are implemented inside the FPGA; the redundant dual-network port Ethernet IP core is not The combination of two single network port IP cores is a redesigned Ethernet IP core with redundant dual...

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Abstract

The invention provides an FPGA based redundant double-network-interface configurable Ethernet IP core capable of adapting to high-stability and high-reliability Ethernet data transmission requirements. The two network interfaces of the FPGA based redundant double-network-interface configurable Ethernet IP core are mutually a primary network interface and a secondary network interface, and have the same MAC address and IP address; the two network interfaces in the working process are connected with the same network respectively through a network line; the Ethernet IP core internally comprises an Ethernet reception module, an Ethernet frame filtering module, a received frame number discrimination module, a reception caching module, an Ethernet transmitted frame packaging module and an Ethernet frame transmission module; the Ethernet frame filtering module is divided into two filtering levels; the received frame number discrimination module is used for discriminating the received frame numbers in the received data frames which satisfy a user filtration rule are continuous so as to detect whether network frame loss occurs in the Ethernet transmission process.

Description

technical field [0001] The invention relates to an FPGA-based Ethernet IP core. Background technique [0002] In today's society, Ethernet-based data communication transmission has penetrated into various fields of our lives. Among them, in video monitoring, due to the reliability and convenience of Ethernet communication, the real-time video monitoring system using Ethernet has been widely used in shopping malls, transportation, industry and other fields. [0003] At present, in an ordinary video monitoring system, a camera has only one network transmission path, and the network camera can be connected to a local area network or the Internet, and a little configuration can realize long-distance real-time video monitoring. However, in practical applications, once the transmission network cable is abnormal, or data frames are lost during transmission, mosaics or black screens will appear on the monitoring screen, which may cause some key video information to be lost. In add...

Claims

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Application Information

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IPC IPC(8): H04L12/24H04L1/22H04L1/18H04L1/16H04L1/00
CPCH04L1/004H04L1/0083H04L1/1607H04L1/1816H04L1/22H04L41/0631H04L41/0663
Inventor 刘广森谢庆胜张辉张海峰任龙冯佳刘庆王华赵晓冬
Owner XI'AN INST OF OPTICS & FINE MECHANICS - CHINESE ACAD OF SCI
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