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A multi-chip synchronous flip-chip mechanism and its packaging process

A multi-chip packaging and chip technology, which is applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., can solve the problems of increasing production costs and reducing work efficiency, reducing flip-chip production costs and improving flip-chip efficiency. , The effect of reducing the difficulty of flipping

Active Publication Date: 2018-06-05
GUANGDONG UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the existing process, the chip flip-chip machine can only complete the flip-chip interconnection of a single chip at a time, which reduces work efficiency and increases production costs.

Method used

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  • A multi-chip synchronous flip-chip mechanism and its packaging process
  • A multi-chip synchronous flip-chip mechanism and its packaging process
  • A multi-chip synchronous flip-chip mechanism and its packaging process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0070] The multi-chip synchronous flip-chip mechanism of this embodiment, such as figure 1 As shown, it includes a crystal-bonding platform 1 and a substrate 2, and the crystal-bonding platform 1 and the substrate 2 are relatively arranged;

[0071] Such as Figure 4 As shown, the working surface of the crystal bonding platform 1 is provided with a plurality of chip fixing parts 11, and the chip fixing parts 11 are grooves 111 or bosses 112;

[0072] Such as figure 1 As shown, when a plurality of chips 4 with the same thickness are flipped, the die bonding platform 1 is provided with a plurality of grooves 111 with the same depth or bosses 112 with the same height;

[0073] Such as figure 2 As shown, when a plurality of chips 4 with different thicknesses are flipped, the die-bonding platform 1 is provided with a plurality of grooves 111 with different depths or bosses 112 with different heights to compensate for the gap between the chips 4. the thickness difference;

[0...

Embodiment 2

[0126] The multi-chip synchronous packaging process of this embodiment, such as Figure 10 shown, including the following steps:

[0127] (1) Coating a layer of temporary bonding glue 3 on the surface of the crystal bonding platform 1, the thickness of the temporary bonding glue 3 is 0.025mm;

[0128] (2) Take chips 4 with the same thickness one by one and place them on the die-bonding platform 1:

[0129] Place the chip 4 with the bump 41 facing up in the groove 111 of the die-bonding platform 1 coated with a layer of temporary bonding glue 3. The die-bonding platform 1 is a square aluminum plate with a length×width of 4mm×4mm and a thickness of 0.2 mm, the array of grooves 111 is 3unit×3unit, the depth of the grooves 111 is the same, and the distance between the grooves 111 is the distance between the chips 4 on the substrate 2;

[0130] (3) Detect the relative position and height uniformity between the 4 chips:

[0131] Use a laser detection instrument to detect the rela...

Embodiment 3

[0141] The multi-chip synchronous packaging process of this embodiment, such as figure 2 shown, including the following steps:

[0142] (1) Coating a layer of temporary bonding glue 3 on the surface of the crystal bonding platform 1, the thickness of the temporary bonding glue 3 is 0.025mm;

[0143] (2) Take chips 4 with different thicknesses one by one and place them on the die-bonding platform 1:

[0144] Place the chip 4 with the bump 41 facing up in the boss 112 of the crystal-bonding platform 1 coated with a layer of temporary bonding glue 3. The crystal-bonding platform 1 is a rectangular glass plate with a length×width of 6mm×5mm and a thickness of 0.25mm, the boss 112 array is 5unit×4unit, the height of the boss 112 is determined according to the thickness of the chip 41, so that the bottom ends of the bumps 41 of all the chips 4 are located in the same plane, and the distance between the bosses 112 is the chip 41 on the substrate 2. put spacing;

[0145] (3) Detec...

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PUM

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Abstract

The invention discloses a multi-chip synchronous flip-chip mechanism and a packaging process thereof. According to the invention, a plurality of chip fixing parts are arranged on the working surface of the die bond platform, wherein the chip fixing parts are grooves or bosses; when a plurality of chips with the same thickness are inversely mounted, a plurality of grooves with the same depth or a plurality of bosses with the same height are arranged on the die bond platform; when a plurality of chips which are not completely identical in thickness are inversely mounted, a plurality of grooves with different depths or a plurality of bosses with different heights are arranged on the die bond platform to compensate the thickness differences among the chips. With the mechanism and the method, it is possible to realize one-time inversion of a plurality of chips, especially a plurality of chips with different thicknesses and sizes; in addition, it is also possible to realize the system-level packaging, or rather, a plurality of chips with different functions, comprising processors and the memories are placed in the same die bond platform so as to realize one-time inversion of the system-level chip set. Therefore, while the inverse mounting quality is guaranteed, the inverse mounting cost and inverse mounting difficulty are reduced greatly and the inverse mounting efficiency is increased substantially.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing technology, in particular to a multi-chip synchronous flip-chip mechanism and packaging technology thereof. Background technique [0002] Bump chip flip-chip soldering is to interconnect the chip with the bump face down to the substrate with solder to form a stable and reliable mechanical connection and electrical connection. Since the chip pads of bump chip flip-chip welding can be arranged in an array, the chip mounting density is high, and it is suitable for LSI and VLSI chips with high I / O counts; The connection method has superior circuit characteristics of high frequency, low delay, and low crosstalk, and is more suitable for high-frequency, high-speed electronic product applications. Therefore, the flip-chip soldering process has been highly valued in microelectronic packaging since its inception. [0003] The existing bump chip flip-chip welding process is to take the chip...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/67H01L21/50
CPCH01L2224/73253
Inventor 崔成强赖韬杨斌张昱
Owner GUANGDONG UNIV OF TECH