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Output clock generation method and device

A technology for outputting clocks and inputting clocks, applied in the field of optical transmission, can solve problems such as the inability to realize seamless switching of clock sources, and achieve the effect of seamless switching

Pending Publication Date: 2017-12-19
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The embodiment of the present invention provides a method and device for generating an output clock to at least solve the problem in the related art that seamless switching of the clock source cannot be realized

Method used

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  • Output clock generation method and device

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0041] The method embodiment provided in Embodiment 1 of the present application can run on figure 1 In the architecture shown, figure 1 It is a structural block diagram of an operating framework of a method for generating an output clock in an embodiment of the present invention. Such as figure 1 As shown, the architecture includes: a central processing unit CPU, a field programmable gate array FPGA, multiple customer ports, multiple line side ports and a frequency multiplication module, wherein the FPGA receives from each customer port and / or line side port Each service recovery clock (input clock), and then select a service recovery clock as an output clock according to a predetermined rule from each of the obtained service recovery clocks. The predetermined rule can be the priority of each service recovery clock, and the priority can be The CPU is configured, and in order to adapt to the service processing of each customer port and / or line side port, it may be necessary to...

Embodiment 2

[0084] In this embodiment, an output clock generation device is also provided, which is used to implement the above embodiments and preferred implementation modes, and what has already been described will not be repeated. As used below, the term "module" may be a combination of software and / or hardware that realizes a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.

[0085] Figure 5 is a structural block diagram of an output clock generating device according to an embodiment of the present invention, such as Figure 5 As shown, the device includes:

[0086] A detection module 52, configured to detect whether the current input clock is valid;

[0087] The selection module 54 is connected with the above-mentioned detection module 52, and is used to select a specified sampling value from a plural...

Embodiment 3

[0113] The embodiment of the invention also provides a storage medium. Optionally, in this embodiment, the above-mentioned storage medium may be configured to store program codes for executing the steps of the method in Embodiment 1.

[0114] Optionally, in this embodiment, the above-mentioned storage medium may include but not limited to: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk Various media that can store program codes such as discs or optical discs.

[0115] Optionally, in this embodiment, the processor executes the steps of the method in Embodiment 1 according to the program code stored in the storage medium.

[0116] Optionally, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementation manners, and details are not repeated in this embodiment.

[0117] Obviously, those skilled in the art shoul...

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PUM

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Abstract

The invention provides an output clock generation method and device. The method comprises the steps that whether a current input clock is valid is detected; under the condition that the current input clock is invalid through detection, a designated sampling value is selected from pre-stored multiple sampling values corresponding to multiple input clocks, wherein the sampling values are values obtained after a local clock performs sampling counting on the input clocks; and an output clock is generated according to the selected designated sampling value and the local clock. Through the output clock generation method and device, the problem that seamless switching between clock sources cannot be realized is solved.

Description

technical field [0001] The present invention relates to the technical field of optical transmission, in particular to a method and device for generating an output clock. Background technique [0002] With the development of 4G and LTE wireless services, and the application of WDM equipment in sinking networking, it is required that WDM equipment can realize high-precision clock time transmission. The wireless service requires time synchronization on the order of microseconds, and the Network Time Protocol (NTP for short) implemented in a basic pure software manner cannot meet the application requirements. In order to achieve the accuracy of wireless service time synchronization, Optical Transport Network (OTN) equipment is required to support a more accurate IEEE 1588 protocol, which is called: Precision Clock Synchronization Protocol Standard for Network Measurement and Control Systems, usually referred to as PTP protocol. [0003] In the process of implementing the PTP p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/20
CPCG06F11/2005G06F11/2023G06F11/20
Inventor 胡大江
Owner ZTE CORP