Nonvolatile static random access memory unit with average 7T1R

A static random storage, 7T1R technology, applied in static memory, information storage, digital memory information, etc., can solve the problems of reducing unit speed, increasing circuit recovery data delay time, etc., to reduce power consumption, reduce leakage current, and easy charging Effect

Active Publication Date: 2017-12-19
ANHUI UNIVERSITY
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this circuit increases the delay time when the

Method used

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  • Nonvolatile static random access memory unit with average 7T1R
  • Nonvolatile static random access memory unit with average 7T1R
  • Nonvolatile static random access memory unit with average 7T1R

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Embodiment Construction

[0030] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0031] Figure 5 A schematic structural view of an average 7T1R non-volatile static random storage unit provided in an embodiment of the present invention; as Figure 5 As shown, it mainly includes: a 1T1R module and a storage unit module; the storage unit module includes: a first pull-up transistor UL, a second pull-up transistor UR, a first pull-down transistor DL, a second pull-down transistor DR, a first A differential input transistor GL, a s...

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Abstract

The invention discloses a nonvolatile static random access memory unit with average 7T1R. In a data reading step, a row-share switching transistor SN is switched on for regulating and optimizing the size of a differential input transistor, which is beneficial to read operation of the unit and increases read margin; in a data writing step, a word line WL is set at high level, a first and a second differential input transistors are switched on, a control line RSW is set at low level and a transistor RSWL is switched off, a unit control line CTRL is set at low level, and the row-share switching transistor SN is switched off, so that discharge path of the unit is broken and nodes inside the unit are easier to charge, and write capacity of the unit is improved and write margin is increased; in a data recovery step, the row-share switching transistor SN is switched off, so that there is no leakage path and further leakage current is reduced, thus reducing power consumption during the data recovery. Because the recovery operation to the circuit is equivalent to write data into the circuit, so that by switching off the SN, the write capacity of the circuit is improved, and naturally, the data recovery capability of the circuit is improved, thereby reducing required time during the recovery.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an average 7T1R non-volatile static random storage unit. Background technique [0002] As society progresses, reliability and stable operation are very important for mobile devices. The non-volatile memory (Non-Volatile Memory, NVM) can prevent the data stored in the unit from being lost when the power is turned off, which ensures the reliability and stability of the operation. Among them, RRAM can significantly improve the durability and data transmission speed. Applying RRAM to the Static Random Access Memory (SRAM) storage unit can make the SRAM storage unit non-volatile, effectively improving the reliability and reliability of the unit. stability. [0003] In order to reduce the power consumption and area of ​​the storage unit on the premise of improving circuit reliability and stability, the prior art mainly includes the following solutions: [0004] (1) if figur...

Claims

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Application Information

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IPC IPC(8): G11C11/417
CPCG11C11/417
Inventor 彭春雨卢文娟黎轩肖松松倪吉祥蔺智挺李正平谭守标吴秀龙陈军宁
Owner ANHUI UNIVERSITY
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