Semiconductor integrated circuit having connection down-lead for bit line interconnection

Abstract

A semiconductor memory is provided that comprises a plurality of memory cell arrays (ALY), each memory cell array (ALY) including bit lines (BL, / BL) and memory cells each constituted by a variable capacitor, the memory cell arrays (ALY) operating at mutually different timings. The bit lines (BL, / BL) of each memory cell array (ALY) are connected to bit lines (BL, / BL) of the other memory cell arrays (ALY) via connecting wires (CW). Accordingly, the actual capacitances of the bit lines (BL, / BL) are the capacitances of bit lines (BL, / BL) of that memory cell array (ALY) itself plus that of the other memory cell arrays (ALY) plus the capacitances of the connecting wires (CW). Therefore, when data is read from the memory cells, the variations in voltage of the bit lines (BL, / BL) caused by the capacitive division can be enlarged. Consequently, the read margin can be prevented from being degraded, and the manufacturing yield of semiconductor memories can be prevented from being degraded. Additionally, since the variations in voltage of the bit lines are enlarged, the data reading time can be shortened.

Description

technical field [0001] The present invention relates to a technique for reliably reading out data from a semiconductor memory in which variable capacitors form individual memory cells. Background technique [0002] Recently, a ferroelectric memory has been developed as a non-volatile semiconductor memory having both the high-speed performance of a DRAM and a flash memory and an EEPROM. For example, each memory cell of a ferroelectric memory has a ferroelectric capacitor and a transfer transistor connecting one end of the ferroelectric capacitor to a bit line. The other end of the ferroelectric memory is connected to a plate line. By making the ferroelectric memory behave like a variable capacitor and taking advantage of the fact that the residual ferroelectric polarization is maintained even if the voltage applied to the ferroelectric capacitor goes to zero, the ferroelectric memory Still able to hold the data. [0003] A read operation of a ferroelectric memory is perfor...

AI Technical Summary

Problems solved by technology

Therefore, the reduction in read margin results in a decrease in yield

In turn, lower yields lead to higher manufacturing costs

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