Half Cycle Delay Circuit

Abstract

The invention discloses a half period time delay circuit. Delay of N half periods is carried out on input digital signals. The half period time delay circuit comprises a phase inverter and N shift units. Each shift unit is equipped with two differential signal input ends and two differential signal output ends. Each shift unit is also equipped with two differential clock input ends. A pair of external differential signals are input into the differential input ends of the first shift unit. The differential output ends of an Nth shift unit output delayed differential signals. The differential output ends and the differential input ends of the other shift units are connected in sequence. An external clock signal is input into the input end of the phase inverter. The external clock signal andthe clock signal output by the phase inverter form a pair of differential clock signals. The differential clock signals are input into the differential clock input ends of the shift units. The N is anatural number greater than 1. According to the half period time delay circuit provided by the invention, the number of field-effect transistors needing to be employed is reduced, the power consumption is reduced, an area occupied by a chip is reduced, and the common-mode noise interference resistance is improved.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a half-period delay circuit for delaying input differential digital signals by N half-periods. Background technique [0002] In some specific integrated circuit applications, such as high-speed data interface circuits, it is usually necessary to delay the digital signal by N / 2 clock cycles, that is, the delay of N half cycles, and the module that realizes the delay of N half cycles is half cycle delay circuit. [0003] At present, the half-cycle delay circuit in the prior art is formed by cascading N D flip-flops, such as figure 1 As shown (taking the case of N=4 as an example), the half-period delay circuit includes four D flip-flops D1, D2, D3, D4. Wherein, the clock input terminal of the odd-numbered D flip-flop is connected to the clock signal CLKN, and the clock input terminal of the even-numbered D flip-flop is connected to the clock signal CLKP (such as figure 1 As sh...

AI Technical Summary

Problems solved by technology

When the value of N is large, the entire circuit needs more MOS transistors, which consumes a large area and power consumption cost

in addition, figure 2 The D flip-flop shown is a single-ended signal input and output, and the single-ended signal has a weak ability to resist external common-mode interference (such as unstable ripple on the power supply), which may easily cause distortion of signal transmission

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