A kind of shift register, gate drive circuit and display device
A technology for shift registers and drive signals, which can be used in static memory, digital memory information, instruments, etc., and can solve problems such as poor shift registers
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Embodiment 1
[0124] by Figure 3a Take the shift register shown as an example, all transistors are N-type transistors; the signal of the reference voltage signal terminal Vref is a low potential signal, and the signal of the first node control signal terminal VN1 is a high potential signal; the corresponding input and output timing diagram is as follows Figure 4a shown. Specifically, choose the Figure 4a There are two stages T1 and T2 in the shown input and output timing diagram; wherein, the T1 stage and the T2 stage respectively correspond to 2s in the period of the signal of the first clock signal terminal CK1. In addition, four stages T11, T12, T13 and T14 in the time of displaying one frame in the T1 stage are selected; and four stages T21, T22, T23 and T24 in the time of displaying one frame in the T2 stage are selected.
[0125] In the T11 stage, Input=1, Reset=0, CK1=1, CK2=0. Since Input=1, both the fifth switch transistor M5 and the eighth switch transistor M8 are turned on....
Embodiment 2
[0137] by Figure 3b Taking the shift register shown as an example, all transistors are N-type transistors; the signal of the reference voltage signal terminal Vref is a low potential signal, the signal of the first node control signal terminal VN1 is the same as the signal of the first clock signal terminal CK1, and the signal of the first node control signal terminal CK1 is the same. The signal of the two-node control signal terminal VN2 is the same as the signal of the second clock signal terminal CK2; the corresponding input and output timing diagram is as follows Figure 4b shown. Specifically, choose the Figure 4b There are two stages T1 and T2 in the shown input and output timing diagram; wherein, the T1 stage and the T2 stage respectively correspond to 2s in the period of the signal of the first clock signal terminal CK1. In addition, four stages T11, T12, T13 and T14 in the time of displaying one frame in the T1 stage are selected; and four stages T21, T22, T23 and...
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