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Laminated connection process for wafer in three-dimensional (3D) NAND flash structure

A technology of wafer and flash memory, which is applied in the field of wafer lamination and connection process, can solve the problems affecting the performance of 3D NAND flash memory structure products, reduce the interface bonding force after lamination and connection, and affect the effect of lamination and connection, etc., to achieve enhanced bonding Combined force, improve product performance, increase the effect of interface bonding force

Active Publication Date: 2018-01-19
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology

[0010] However, in the above process, the flattened connection surface 2 is very smooth, so that the connection surfaces are subjected to great resistance when they are close to each other and combined, and at the same time, the bonding force of the interface after the superposition connection will be reduced, thereby affecting the superposition connection. effect, and ultimately affect the product performance of the 3D NAND flash memory structure

Method used

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  • Laminated connection process for wafer in three-dimensional (3D) NAND flash structure
  • Laminated connection process for wafer in three-dimensional (3D) NAND flash structure
  • Laminated connection process for wafer in three-dimensional (3D) NAND flash structure

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Embodiment Construction

[0032] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as ch...

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Abstract

The invention provides a laminated connection process for a wafer in a three-dimensional (3D) NAND flash structure. The laminated connection process comprises the following steps of providing two wafer structures; performing pre-processing, in which laminated connection surfaces of the two wafer structures are pre-processed so as to make the laminated connection surfaces roughed; and laminating the laminated connection surfaces of the two wafer structures, and connecting the two wafer structures to form an integrated structure. By plasma processing on the laminated connection surfaces, relatively rough laminated connection surfaces are obtained so as to increase an interface bonding force after laminated connection; ion doping is performed on the laminated connection surfaces by ion injection, and the contact resistance of a conductive medium among the laminated connection surfaces is reduced; by annealing the integrated structure after laminated connection, and ion diffusion of an interface is accelerated, so that the interface bonding force after laminated connection is increased; by the process, the bonding force of connection interfaces of a plurality of laminated wafers can beincreased, and the product performance of the 3D NAND flash structure is further improved.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND flash memory structure and a manufacturing method thereof, in particular to a superposition of wafers capable of enhancing the bonding force during wafer connection in the 3D NAND flash memory structure and reducing the contact resistance of conductive media Connection process. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11524H01L27/11551H10B41/35H10B41/20
Inventor 张坤刘藩东夏志良
Owner YANGTZE MEMORY TECH CO LTD
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