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Storage array block and semiconductor memory

A storage array and array technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problem that the signal quality of the signal line cannot be effectively improved, and achieve the effect of reducing the size, offsetting the effect of time delay, and speeding up the response

Pending Publication Date: 2018-01-23
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, simply increasing the size of the driver cannot effectively improve the signal quality of the signal line

Method used

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  • Storage array block and semiconductor memory
  • Storage array block and semiconductor memory
  • Storage array block and semiconductor memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] see Figure 4-5 , which are respectively a schematic diagram of signal lines and a schematic diagram of a driving mode of the memory array in the first embodiment. Embodiment 1 of the present invention provides a memory array block 200, including: a plurality of memory array parts 210 distributed in an array, a plurality of row loads 230, a plurality of column signal lines (YS) 240, and row signal lines (RS) 250 , the first signal line driving unit 260 and the second signal line driving unit 270 .

[0055] Wherein, a plurality of array loads 220 distributed laterally are arranged inside each storage array unit 210 .

[0056] The plurality of row loads 230 are respectively connected to the plurality of memory array units 210 .

[0057] The plurality of column signal lines 240 are connected to the plurality of array loads 220 longitudinally distributed along a straight line.

[0058] The row signal lines 250 are respectively connected to the plurality of row loads 230 ...

Embodiment 2

[0065] Embodiment 2 of the present invention is modified on the basis of Embodiment 1, and another implementation mode is provided, that is, only a plurality of column signal line drivers are provided on the second signal line driving unit, and the load on the column signal line is controlled at the same time. drive. The specific plan is described as follows:

[0066] see Figure 7 , which is a schematic diagram of signal lines of the memory array according to Embodiment 2 of the present invention. Embodiment 2 of the present invention provides a memory array block 300, including: a plurality of memory array parts 210 distributed in an array, a plurality of row loads 230, a plurality of column signal lines 240, a row signal line 250, a first signal line driver unit 260 and the second signal line driving unit 270 .

[0067] The connection relationship of the devices inside the memory array block 300 in the second embodiment is the same as that in the first embodiment, and wi...

Embodiment 3

[0073] Embodiment 3 of the present invention is modified on the basis of Embodiment 1, and another implementation is provided, that is, only the row signal line driver is provided on the second signal line driving unit, and the load on the column signal line is driven at the same time. The specific plan is described as follows:

[0074] see Figure 8 , which is a schematic diagram of signal lines of a memory array according to Embodiment 3 of the present invention. Embodiment 3 of the present invention provides a memory array block 400, including: a plurality of memory array units 210 distributed in an array, a plurality of row loads 230, a plurality of column signal lines 240, a row signal line 250, a first signal line driver unit 260 and the second signal line driving unit 270 .

[0075] The connection relationship of the devices in the memory array block 400 in the third embodiment is the same as that in the first embodiment, and will not be repeated here. The difference...

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Abstract

The invention provides a storage array block. The storage array block comprises a plurality of storage array parts which are distributed in an array, a plurality of row-directional loads, a pluralityof strips of signal wires, a row signal wire, a first signal wire driving unit and a second signal wire driving unit, wherein each storage array part is internally provided with a plurality of array loads which are transversely distributed; the row-directional loads are connected with the plurality of storage array parts respectively; the signal wires are connected with the plurality of array loads which are longitudinally distributed along the straight line; the row signal wire is connected with the plurality of row-directional loads respectively; the first signal wire driving unit is connected with a plurality of strips of line signal wires and the row signal wire respectively; the second signal wire driving unit is connected with the row signal wire and / or the plurality of strips of line signal wires respectively. According to the storage array block provided by the invention, two ends are driven simultaneously so that the size of a single driving unit can be reduced. Furthermore, the response of a long / heavy-load signal wire also can be accelerated and time delaying influences of the long wire are cancelled, so that rapid control and time sequence optimization of a long / heavy-load signal are realized.

Description

technical field [0001] The invention relates to the technical field of semiconductor storage, in particular to a storage array block and a semiconductor storage. Background technique [0002] In memory devices, long / heavy load signal lines can be seen everywhere, and their driving circuits and driving methods often become one of the key points in timing and chip size design. [0003] When a signal line is very long and drives many loads, the size of the output stage device of this signal driving circuit is often large, and the time delay of different segments of this signal line is also very different, which usually gives The timing design and size optimization of the circuit brings many difficulties. [0004] Such as Figure 1-2 As shown in FIG. 2 , they are respectively a schematic diagram of signal lines and a schematic diagram of a driving method for storing an entire column in a dynamic random access memory (DRAM) in the background technology. The storage array block ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/18G11C7/12G11C8/14G11C8/08
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC