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General-purpose parallel computing architecture

A parallel computing and communication line technology, applied in the field of general parallel computing architecture, can solve problems such as mismatched brain connectivity or three-dimensional structure, insufficient

Active Publication Date: 2018-01-26
GOLDMAN SACHS & CO LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, conventional attempts to simulate the human brain or design computing systems that rival the capabilities of the human brain have generally been inadequate for a number of reasons, such as substantially mismatching the brain's connectivity or three-dimensional structure.

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Embodiment Construction

[0016] discussed below Figure 1A to Figure 9 And the various embodiments used to describe the principles of the invention in this patent document are by way of illustration only and should not be construed in any way as limiting the scope of the invention. Those skilled in the art will understand that the principles of the invention may be implemented in any type of suitably arranged device or system.

[0017] As noted above, the human brain is a massively parallel system typically containing approximately 100 billion neurons connected by 1000 trillion synapses. Synapses support the transmission of signals between neurons. The structure of the human brain is very different from a classical Turing machine. Given the typically large number of neurons and synapses in the human brain, it is impractical to simulate the human brain using a classical Turing machine.

[0018] While many branches of human intelligence exist, a key branch is dimensionality reduction, which refers to...

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Abstract

An apparatus includes multiple parallel computing cores (102), where each computing core (102) is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple parallel coprocessors (112) associated with each computing core (102). The apparatus further includes multiple communication lines (122, 124) configured to transport the input data from each computing core (102) to a designated one of the coprocessors (112) associated with each of the computing cores (102), where the coprocessors (112) are configured to process the input data and generate output data. In addition, the apparatus includes multiple reducer circuits (115), where each computing core (102) is associated with one of the reducer circuits (115). Each reducer circuit (115) is configured to receive the output data from each of the coprocessors (112) of the associated computing core (102), to apply one or more functions to the output data, and to provide one or more results to the associated computing core (102).

Description

technical field [0001] The present disclosure generally relates to hardware architectures for computing devices and computing systems. More specifically, the present disclosure relates to a general parallel computing architecture that can support advanced computing functions, such as those used in artificial intelligence. Background technique [0002] The human brain is a massively parallel system typically containing about 100 billion neurons connected by one quadrillion synapses. Ideally, mimicking the operation of the human brain could support advanced computing functions, such as artificial intelligence. However, traditional attempts to simulate the human brain, or to design computing systems that rival the capabilities of the human brain, have generally been inadequate for a number of reasons, such as substantially mismatching the brain's connectivity or three-dimensional structure. Contents of the invention [0003] The present disclosure provides a general paralle...

Claims

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Application Information

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IPC IPC(8): G06F15/80G06F9/50
CPCG06F15/8023G06F9/5072G06F15/17318G06N3/063G06F15/80
Inventor P.伯查德U.德雷珀
Owner GOLDMAN SACHS & CO LLC