Measuring Method of Effect of Surface State Traps on Device Output Characteristics

Abstract

The present invention discloses a measurement method for an influence of a surface state trap on device output characteristics. The objective of the invention is to mainly solve a problem that an influence of a surface state trap on device output characteristics cannot be individually measured in the prior art. The implementation scheme of the method comprises the steps of: newly making a gate between a source and a drain of a measured device to form a double-gate structure; measuring an output current of the device; applying a pulse voltage to fill a surface state trap of the device; and after the filling is complete, stopping applying of the pulse voltage, measuring the output current of the device, and calculating and obtaining an influence of the surface state trap of the device on thedevice output characteristics. The measurement method for influence of a surface state trap on device output characteristics is simple in test circuit and reliable in test result, can be used for researching a current collapse effect of a device and can further improve technology optimization and reliability analysis of the device.

Description

technical field [0001] The invention belongs to the technical field of microelectronic testing, in particular to a method for measuring output characteristics of devices, which can be used for process optimization and reliability analysis of devices. Background technique [0002] From the first generation of semiconductor materials represented by silicon materials and the second generation of semiconductor materials represented by gallium arsenide materials to the third generation of semiconductor materials represented by gallium nitride, the devices made of them are more and more used more extensive. [0003] As the device is gradually becoming practical, the reliability of the device has become an important research direction. Especially in high-frequency and high-power applications, the output current of the device decreases, resulting in a decrease in output power density. This phenomenon is called the current collapse effect. Since the current collapse phenomenon was ...

AI Technical Summary

Problems solved by technology

The virtual gate model believes that the electrostatic suppression of the two-dimensional electron gas by the electrons trapped by the surface states of the device and barrier layer traps leads to a decrease in the output power density

[0004] The traditional method of measuring the current collapse of a device is to use a semiconductor parameter analyzer to perform a DC or pulse test on the device. By comparing the maximum output current under different pulse voltages and DC voltages, the current collapse is obtained. However, the result measured by this method is that the device The influence of both surface state traps and barrier layer traps on the output characteristics of the device cannot be studied only on the influence of surface state traps on the output characteristics of the device, but the single study of the influence of device surface state traps on the output characteristics of the device is very important for the study of the current collapse effect. The mechanism and process optimization of the device and the improvement of reliability are crucial, so there is an urgent need for a measurement method to study the influence of surface state traps on the output characteristics of the device

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