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Semiconductor structure forming method

A semiconductor and isolation structure technology, applied in the field of semiconductor structure formation, can solve the problems affecting the performance of fin field effect transistors and increasing the difficulty of the process, so as to reduce the impact, improve the performance and reduce the possible effects of damage

Inactive Publication Date: 2018-03-09
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] As the size of semiconductor devices shrinks, the distance between adjacent fins decreases, and the difficulty of forming an isolation layer between adjacent fins increases, which affects the performance of the formed fin field effect transistor.

Method used

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  • Semiconductor structure forming method

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Embodiment Construction

[0032] It can be seen from the background art that there are performance problems in the FinFET in the prior art. The reasons for its performance problems are analyzed in conjunction with the formation process of FinFETs:

[0033] As the size of semiconductor devices shrinks, the size of transistors shrinks, and the distance between adjacent fin field effect transistors also shrinks. Stress layers of adjacent FinFETs are prone to merge, thereby causing bridging between source regions and drain regions of adjacent FinFETs. In order to prevent bridging between the source region and the drain region of adjacent FinFETs, a single diffusion break (Single diffusion break, SDB) structure is introduced in the prior art.

[0034] refer to Figure 1 to Figure 7 , shows a schematic diagram of a cross-sectional structure corresponding to each step of a method for forming a semiconductor structure.

[0035] refer to figure 1 and figure 2 ,in figure 2 yes figure 1 Schematic diagra...

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Abstract

A semiconductor structure forming method comprises steps: a substrate is formed, wherein the substrate is provided with multiple first fin parts and multiple second fin parts; first isolation structures and second isolation structures are formed; protection layers are formed, wherein the process temperature is less than 780 DEG C during the protection layer forming process; and the second isolation structures are back etched to expose partial side wall surfaces of the first fin parts and the second fin parts. In the technical scheme of the invention, during the step of forming the protection layers located on the first isolation structures, the process temperature is less than 780 DEG C. The process temperature for forming the protection layer is low, influences on the semiconductor structure by the protection layer forming process can be effectively reduced, the possibility that the semiconductor structure is damaged is reduced, and the performance of the formed semiconductor structure is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The ability of traditional planar transistors to control channel current Weakened, resulting in short channel effect, resulting in leakage current, and ultimately affecting the electrical performance of semiconductor devices. [0003] In order to overcome the short-channel effect of the transistor and suppress the leakage current, a Fin Field Effect Transistor (FinFET) is proposed in the prior...

Claims

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Application Information

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IPC IPC(8): H01L21/8234H01L21/762
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP
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