Wafer surface appearance control system and control method

A surface topography and control method technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve process defects such as wafer surface topography changes exceeding process specifications, wafer exposure, etc., and automatically adjust wet etching etc. to achieve good surface morphology and avoid defects
CN107946191AInactive Publication Date: 2018-04-20HUAIAN IMAGING DEVICE MFGR CORP

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
HUAIAN IMAGING DEVICE MFGR CORP
Publication Date
2018-04-20
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention provides a wafer surface appearance control system and control method. The wafer surface appearance control method comprises the following steps of 1) providing a wafer; 2) performing chemical mechanical polishing on the surface of the wafer; 3) setting etching time according to removal conditions in different regions of the wafer surface in the chemical mechanical polishing process;and 4) performing etching on different regions of the wafer surface according to the etching time. The wet etching time for the wafer is set according to the removal conditions in different regions of the wafer surface in the chemical mechanical polishing process, and the appearance deviation of the wafer surface caused in the chemical mechanical polishing process in the wet etching process can be compensated, so that the wet etched wafer has high surface appearance, the wafer surface appearance is effectively controlled within the reasonable technological specifications, and generation of defects in the subsequent process can be avoided.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to the technical field of semiconductors, in particular to a wafer surface topography control system and control method. Background technique

[0002] The chemical mechanical polishing (CMP) process is a very important process in the semiconductor field at present, and it is widely used to correct the flatness of the wafer surface. However, after the wafer is chemically mechanically polished, there will be certain changes in the surface of the wafer, such as figure 1 As shown, the thickness of different regions on the wafer surface will vary. In the follow-up wet etching process, the existing method adopted is to spray etching liquid in the wafer with constant wet etching process parameters (for example, the etching time of different regions of the wafer, etc.). The surface of the wafer is etched, and the process parameters of wet etching are not automatically adjusted according to the wafer morphology after chemical mechanical ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More