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Semiconductor integrated circuit and semiconductor device including the same

An integrated circuit and semiconductor technology, applied in the field of semiconductor devices, can solve problems such as gate breakdown of MOS transistors, and achieve the effect of preventing transistor breakdown

Pending Publication Date: 2018-04-27
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, the problem is that the gate of this MOS transistor is broken down

Method used

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  • Semiconductor integrated circuit and semiconductor device including the same
  • Semiconductor integrated circuit and semiconductor device including the same
  • Semiconductor integrated circuit and semiconductor device including the same

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0028] figure 1 is a block diagram showing a configuration example of the semiconductor integrated circuit 1 according to the first embodiment. The semiconductor integrated circuit 1 according to the present embodiment can simply use a small-scale secondary clamp circuit to prevent transistors receiving signals transmitted between circuit blocks driven by different power sources gate breakdown. This will be described in detail below.

[0029] Such as figure 1 As shown, the semiconductor integrated circuit 1 includes a circuit block 11, a circuit block 12, a clamp circuit 13, a clamp circuit 14, a clamp circuit 15, a trigger circuit 16, and a transistor Tr1. The clamp unit 18 is formed by the clamp circuits 13 and 14 . As for the primary clamp circuits 13 to 15 , the secondary clamp 17 is formed by the trigger circuit 16 and the transistor Tr1 .

[0030] For example, the semiconductor integrated circuit 1 is provided in a small-scale analog IP (intellectual property) are...

no. 2 example

[0107] Figure 11 is a block diagram showing a configuration example of the semiconductor integrated circuit 2 according to the second embodiment. The semiconductor integrated circuit 1 has a configuration that protects transistors in the circuit block 12 that receive the different power supply crossing signal S1 from ESD breakdown. The semiconductor integrated circuit 2 has a configuration that protects transistors in the circuit block 11 that receive the different power supply crossing signal S2 from ESD breakdown. It will be described below.

[0108] The semiconductor integrated circuit 2 includes a secondary clamp circuit 27 instead of the secondary clamp circuit 17 of the semiconductor integrated circuit 1 . The secondary clamp circuit 27 has a transistor Tr2 and a trigger circuit 16 . The transistor Tr2 is provided between the different power supply crossing signal line S2 and the power supply voltage line VDD1 , and is turned on / off according to a trigger signal Strg...

no. 3 example

[0117] Figure 13 is a block diagram showing a configuration example of the semiconductor integrated circuit 3 according to the third embodiment. Unlike the semiconductor integrated circuit 1 , the semiconductor integrated circuit 3 also includes a regulator 19 . Instead of the secondary clamping circuit 17 , it also includes a secondary clamping circuit 37 .

[0118] The regulator 19 generates a predetermined stable internal voltage VINT from the power supply voltage VDD1. The line to which the internal voltage VINT is supplied will be referred to as an internal voltage line VINT hereinafter. In this case, the circuit block 11 is provided between the internal voltage line VINT and the reference voltage line VSS1. That is, the circuit block 11 is driven by the internal voltage VINT and the reference voltage VSS1.

[0119] The secondary clamp circuit 37 has a transistor Tr1 and a trigger circuit 16 . Trigger circuit 16 is provided between power supply voltage line VDD1 and...

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PUM

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Abstract

The application relates to a semiconductor integrated circuit and a semiconductor device including the same. According to an embodiment, a semiconductor integrated circuit includes a circuit block provided between a power source voltage line and a reference voltage line, a circuit block provided between a power source voltage line and a reference voltage line, a clamp unit which is provided between the power source voltage line and the reference voltage line and is conductive when it is detected that an ESD voltage is applied using a first time constant, a trigger circuit which causes a trigger signal to be active when it is detected that an ESD voltage is applied using a second time constant smaller than the first time constant, and a transistor which is provided between a signal line between the circuit blocks, and the power source voltage line or the reference voltage line.

Description

[0001] Cross References to Related Applications [0002] The entire disclosure of Japanese Patent Application No. 2016-205890 filed on October 20, 2016 including specification, drawings and abstract is hereby incorporated by reference. technical field [0003] The present invention relates to a semiconductor integrated circuit and a semiconductor device including the semiconductor integrated circuit, for example, to a semiconductor integrated circuit suitable for preventing transistor breakdown due to generation of electrostatic discharge and a semiconductor device including the semiconductor integrated circuit. Background technique [0004] In a semiconductor device, an ESD (Electrostatic Discharge) protection circuit for preventing electrostatic discharge is provided. ESD discharge models include HBM (Human Body Model), MM (Machine Model) and CDM (Charged Device Model). HBM is a model of electrostatic discharge generated by discharging charges charged to the human body t...

Claims

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Application Information

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IPC IPC(8): H01L27/02
CPCH01L27/0251H01L27/0296H02H9/046H03K5/08
Inventor 成田幸辉
Owner RENESAS ELECTRONICS CORP