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Chip package structure and manufacturing method thereof

A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., and can solve problems such as reduced yield reliability, reduced productivity, and increased production costs

Active Publication Date: 2018-05-01
POWERTECH TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, it will often result in a decrease in yield or reliability, as well as decrease in throughput and increase in production cost.

Method used

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  • Chip package structure and manufacturing method thereof
  • Chip package structure and manufacturing method thereof
  • Chip package structure and manufacturing method thereof

Examples

Experimental program
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Embodiment approach

[0069] refer to Figure 1E , forming the first sealing material 161 (shown in Figure 1D ) Afterwards, the wiring 152 (shown in Figure 1D ) protruding from the support frame surface 140 a of the support frame 140 is removed to form the first conductive connecting member 150 . In this way, the top surface 150 b of the first conductive connecting member 150 can be substantially flush with the surface 140 a of the branch frame 140 . Through the foregoing exemplary implementations, the first conductive connection member 150 in this embodiment may be a stud bump formed by a wire bonding machine. In other words, compared with the diameter 150a of the portion of the first conductive connecting member 150 away from the circuit carrier 110 , the connection terminal 151 a of the first conductive connecting member 150 connected to the circuit carrier 110 has a larger width.

[0070] In this embodiment, if the first sealing material 161 is further covered on the branch frame surface 1...

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PUM

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Abstract

The invention provides a chip package structure and a manufacturing method thereof. A chip package structure comprises a substrate, a first chip, a frame, a plurality of first conductive connectors, afirst encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposedon the frame and is electrically connected to the substrate via the first conductive connectors.

Description

technical field [0001] The invention relates to a chip packaging structure and a manufacturing method thereof, in particular to a chip packaging structure with a branch frame and a manufacturing method thereof. Background technique [0002] In recent years, electronic devices that meet market demands and improvements in manufacturing technology are booming. Considering the portability of 3C electronic products such as computers, communications, and consumers, as well as their growing demands, the traditional single-chip packaging structure has gradually failed to meet the needs of the market. That is to say, when designing products, the trends of lightness, thinness, shortness, smallness, compactness, high density and low cost must be considered. Therefore, in view of the demand for lightness, thinness, shortness, smallness and compactness, stacking integrated circuits (integrated circuits; ICs) with various functions in different ways to reduce the size and thickness of pa...

Claims

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Application Information

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IPC IPC(8): H01L23/498H01L23/495H01L25/065H01L21/60
CPCH01L23/49541H01L23/49816H01L24/81H01L25/0657H01L2224/81007H01L2224/16225H01L2224/73253H01L2924/15311
Inventor 王启安徐宏欣
Owner POWERTECH TECHNOLOGY
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