Preparation method of 3d NAND wiring hole including silicon-rich silicon nitride isolation dielectric layer

Abstract

Provided is a method for preparing a 3D NAND wire hole, the wire hole is formed in a string selection region, and the wire hole is filled with tungsten metal to realize wire connection, and a silicon-nitrogen-rich compound is deposited in the wire hole before the pre-cleaning step The silicon oxide layer is used as the isolation dielectric layer. In the above preparation method, the traditional silicon nitride deposition is replaced by a silicon-rich silicon nitride layer deposition process, thereby reducing the 3 The problem of uneven upper and lower layers of the isolation dielectric layer in the wire hole caused by the decomposition or reaction of the wire hole, thereby avoiding the etching problem caused by the uneven distribution of the isolation dielectric layer, and improving the stability and reliability of the process.

Description

technical field [0001] The present application relates to the technical field of three-dimensional (3D) memory, and more specifically, relates to a preparation method of a 3D NAND wiring hole including a silicon-rich silicon nitride isolation dielectric layer. Background technique [0002] With the rapid development of flash memory, the structure of 3D flash memory has been developed rapidly, and NAND flash memory is a better storage device than hard disk drives. As people pursue non-volatile storage products with low power consumption, light weight and good performance , 3D NAND flash memory has been widely used in electronic products. [0003] In the 3D NAND structure, in the current process, a plurality of wire holes are formed by multiple etching in the SS (string selection) region, and metal tungsten is filled in the wire holes by chemical vapor deposition (CVD), so as to realize wire connection, Figure 1(a) and 1(b) Schematic diagrams of wire holes and tungsten wire...

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Problems solved by technology

The above-mentioned thickness distribution of the SiN layer has a certain influence on the subsequent etching of SiN at the bottom of the wire hole, so that the etching of the SiN layer requires more energy or time, and due to the high hardness of SiN, in step 3 (c) The etching energy required to open the deposited SiN at the bottom is relatively large, which will increase the probability of excessive etching, so that the metal W at the bottom will be damaged, which will bring certain stability and reliability to the process. difficulty

according to Figure 5 The energy dispersive spectroscopy (EDS) map shown after bottom etching shows that the SiN layer prepared by the prior art will have obvious nitrogen residues after bottom etching

and Image 6 Then it shows the lead hole after over-etching, such as Image 6 The wire hole shown in the dotted box, due to over-etch, can cause wire connection errors and affect the electrical performance of the device

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