Manufacturing method of fin field effect transistors

Abstract

The invention provides a manufacturing method of fin field effect transistors. The method comprises the steps of providing an SOI substrate and forming a step part on the SOI substrate; forming fins of different heights on the basis of the step part of the SOI substrate; forming a gate dielectric layer on the surfaces of the fins and forming gates on the surface of the gate dielectric layer; and carrying out ion implantation on two sides of the fins separately by adopting a tilt-angle implantation mode to form source regions and drain regions on the fins. According to the manufacturing methodof the fin field effect transistors, the shadow effect of the fins of adjacent fin field effect transistors can be avoided.

Description

【Technical field】 [0001] The invention relates to the technical field of semiconductor chip manufacturing, in particular to a method for manufacturing a fin field effect transistor. 【Background technique】 [0002] A Fin Field Effect Transistor (FinFET) is a field effect transistor with a fin-shaped channel structure. In a fin field effect transistor, a fin (Fin) is vertically formed on the surface of a silicon substrate, and the fin serves as a channel, and the gate controls the channel by covering the surface of the fin. [0003] In the manufacturing process of FinFET, when the source region and the drain region of the FinFET are implanted with ions, it is required to implant ions on the top and side of the fin. Generally speaking, the FinFET The fins of the transistor are high and narrow, so the ion implantation of the source region and the drain region is usually carried out by oblique angle ion implantation. However, in an actual chip, there are often situations where ...

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Problems solved by technology

However, in an actual chip, there are often situations where multiple fin field effect transistors are densely arranged. At this time, due to the influence of adjacent fins, the source and drain regions of multiple fin field effect transistors of the chip are simultaneously processed. During implantation, adjacent fin field effect transistors are prone to the influence of implant shadow effects, that is, the fins of fin field effect transistors will block the inclined angle ion implantation path of the source and drain regions of adjacent fin field effect transistors

[0004] For the above situation, the conventional solution is to increase the spacing between adjacent fin field effect transistors. However, although the method of increasing the spacing can solve the shadow effect of source and drain injection, it will waste the chip area and affect the integration of the chip. , increase the overall cost of the chip

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