37results about How to "Increase critical size" patented technology

The invention relates to a design of fanout trace in a TFT-LCD (thin film transistor-liquid crystal display) narrow frame design. The design of the fanout trace mainly comprises a first metal layer of first fanout traces and a second metal layer of second fanout traces, wherein the first fanout traces are used for etching to form parallel arrangement; the second fanout traces are used for etching to form another parallel arrangement; the first metal layer and the second metal layer are configured in an up-down parallel manner and are opposite substantially; the width and the fanout pitch of the first fanout traces are equal to the width and the fanout space of the second fanout traces; and projections of the first fanout traces on the second metal layer are in parallel to the second fanout traces and are staggered with the second fanout traces at equal distances. By utilizing the design of the fanout trace in the TFT-LCD narrow frame design, the trace pitch can be less than or equal to 8 micrometers, the fanout height is reduced, metal critical dimensions are increased, the resistance load is reduced, and the narrow frame design is realized.

The invention provides an array substrate and a touch display panel comprising the array substrate. The array substrate comprises a substrate, multiple switch elements located above the substrate, a first insulation layer located above the switch elements and provided with an upper surface having at least one recess, a touch-control electrode layer located above the switch elements and provided with multiple touch-control electrodes, and a touch-control wiring layer located above the first insulation layer and provided with multiple touch-control wiring. Each touch-control wiring is electrically connected with each touch-control electrode correspondingly and used for connecting a corresponding touch-control electrode to a driving circuit. At least one touch-control wiring comprises at least one protrusion arranged in a corresponding recess. The array substrate and the touch display panel comprising the array substrate help improve display effect.

The embodiment of the invention provides a pixel circuit and a driving method thereof, an array substrate and a display device, relates to the technical field of display, and can improve the display effect. The pixel circuit comprises a first sub-pixel circuit and a second sub-pixel circuit, each of the first sub-pixel circuit and the second sub-pixel circuit comprises a reset sub-circuit, a write-in compensation sub-circuit, a driving sub-circuit, a light-emitting control sub-circuit and a light-emitting device; the reset sub-circuit is configured to input the voltage provided by the initialvoltage end to the driving sub-circuit under the control of the first reset control end; the write-in compensation sub-circuit is configured to write a signal output by the data end into the driving sub-circuit under the control of the write-in control end so as to perform threshold voltage compensation on the driving sub-circuit; and the light-emitting control sub-circuit is configured to conducta current path between the first power supply voltage end and the second power supply voltage end under the control of the enabling end, and transmit the driving current provided by the driving sub-circuit to the light-emitting device.

The invention provides a method for improving etched via bottom critical dimension (VBCD) of a 40 nm dual damascene structure. The method comprises the following steps: etching a groove, forming a protective layer of side walls of a ULK (Ultra-low dielectric constant) layer, and forming vias of an exposed metal layer. According to the method provided by the invention, the side walls of the ULK layer can be protected, and the VBCD can be enlarged in the step for etching the groove in the 1*DD AIO (all in one) process.

The invention relates to an embedded flash memory, a preparation method thereof, and an electronic device. The method comprises that a substrate is provided, an active region isolated by a shallow trench isolation (STI) oxide is formed in the substrate, and the top of the STI oxide is higher than the surface of the substrate; a floating gate material layer is deposited to cover the active region and the STI oxide; the floating gate material layer is flattened to expose the surface of the STI oxide; the floating gate material layer is etched back to reduce the thickness of the floating gate material layer and expose the STI oxide of certain height; the exposed STI oxide is etched back to reduce the key size of the exposed STI oxide; the floating gate material layer is re-deposited till the top of the STI oxide to surround the STI oxide and flatten the floating material layer; and the part whose key size is reduced of the STI oxide is removed to form a T-shaped floating gate on the active region.

The invention provides a touch display panel, which comprises a first substrate, a thin-film transistor, a pixel electrode layer and a common electrode layer, wherein the thin-film transistor is arranged on the first substrate; the pixel electrode layer is arranged on the thin-film transistor and is connected with a drain or a source of the thin-film transistor through a contact hole; the common electrode layer is arranged on the first substrate and below the pixel electrode layer, and is divided into a plurality of common electrodes; a slit is formed between each two adjacent common electrodes; and the slits are connected with contact holes in the slits. According to the touch display panel provided by the invention, the touch detection capability and the display effect are improved.

The invention relates to a preparation method for a motion sensor. The method includes: providing a base, on which a CMOS device is formed; forming a bottom electrode on the base and an MEMS substrate positioned above the bottom electrode, and forming a cavity between the bottom electrode and the MEMS substrate; etching the MEMS substrate to the bottom electrode to form a deep through hole, thereby exposing the bottom electrode; etching the top of the deep through hole to expand the key size of the deep through hole top opening; forming an insulation layer on the side wall of the deep through hole; and depositing a metal material in the deep through hole, and then conducting etching to remove the metal material deposited at the deep through hole top so as to maintain a large key size of the opening. According to the method provided by the invention, no hole is formed in the filling process, and the device yield is improved.

The invention relates to a preparation method of a semiconductor device. The method comprises: providing a semiconductor substrate; forming a virtual gate on the semiconductor substrate; forming a first offset side wall and a second offset side wall at the side of the virtual gate; removing the virtual gate; and removing the first offset side wall to form a groove with the increased critical dimension. According to the invention, after the virtual gate is formed, a thermal treatment oxide layer, the first offset side wall, and the second offset side wall are formed on the virtual gate; and after LDD and source-drain ion injection are executed, the thermal treatment oxide layer and the first offset side wall are removed to form the groove, wherein the critical dimension of the groove is the critical dimension of the metal gate and the critical dimension of the metal gate is larger than that of the conventional metal gate. Moreover, the thermal treatment oxide layer and the first offset side wall are formed after the source-drain ion injection, so that the large critical dimension is obtained and the shadow effect can be avoided and thus the device performance is improved.

The invention provides a method for improving homogeneity of critical dimension of a photomask. The method comprises the steps of: firstly, carrying out initial mask layout design; secondly, dividing the designed initial mask layout to blocks; thirdly, calculating the density of an exposure figure of each block of the initial mask layout; fourthly, determining the adjustment range of the critical dimension of each block according to the density distribution of the exposure figure in the peripheral area of each block; fifthly, adjusting the critical dimension of each block according to the determined adjustment range of the critical dimension of each block, thereby obtaining an updated mask layout; and sixthly, manufacturing a mask according to the updated mask layout.

The invention provides a channel hole etching technology adopting a novel hard mask. The technology comprises the steps that metal aluminum is adopted on a buffer oxide (buffer OX) on a stacking structure as a hard mask layer; the thickness of the metal aluminum hard mask layer is 500 , and before etching, chlorine (Cl2) is adopted for etching to open the metal aluminum hard mask layer; then, oxygen is adopted on the metal aluminum hard mask layer for perform short-time oxidation treatment to form an aluminum oxide (Al2O3) protective layer; then, channel hole etching is performed to form channel holes; finally, boron chloride (BCl3) is adopted for removing the Al2O3 protective layer. The metal aluminum hard mask is not damaged by etching, the thickness can be greatly lowered, and thereforethe problem that the channel hole deforms and some channel holes are closed or lost can be solved; the channel hole arc-shaped bent morphology is improved, and the bottom critical dimension (CD) is enlarged.

The invention discloses a method for reducing polycrystalline silicon critical dimension loss caused by photoetching photoresist reworking, which comprises the steps of S1, providing a semiconductor device for polycrystalline silicon LEC etching, wherein the just preceding process of polycrystalline silicon thin film etching is completed; S2, carrying out polymer deposition; and S3, carrying out photoetching photoresist reworking, and carrying out polycrystalline silicon thin film etching to obtain a polycrystalline silicon critical dimension device meeting the process control standard. According to the method, polymer deposition is carried out on the semiconductor device which is subjected to the just preceding process of etching the polycrystalline silicon thin film, the critical dimension of a hard mask is increased, and under the condition that the pattern of the polycrystalline silicon thin film is not changed, the problem that the critical dimension of polycrystalline silicon is reduced can be effectively solved, the product yield is improved, and the production cost is reduced.

The invention provides a three-dimensional memory and a preparation method thereof. The method comprises the following steps: forming a storage laminated structure on a substrate and forming a storage channel structure penetrating through the storage laminated structure; forming a selection laminated structure laminated on the storage laminated structure and a selection channel structure penetrating through the selection laminated structure and connected with the storage channel structure, wherein the size of the selection channel structure is smaller than that of the storage channel structure on a plane parallel to the substrate; and forming a top selection gate cut structure penetrating through the selection laminated structure. According to the three-dimensional memory and the preparation method thereof, the process window of the top selection gate notch structure formed between the selection channel structures can be increased, and the unit memory density can be improved.

The invention provides a manufacturing method of a semiconductor device, the semiconductor device and an electronic device. The manufacturing method comprises the steps of: providing a semiconductor substrate, wherein a plurality of interlayer dielectric layers and virtual dielectric layers which are laminated in a staggered manner are formed on the semiconductor substrate, each virtual dielectric layer is formed between the adjacent interlayer dielectric layers, grooves are formed in the interlayer dielectric layers and the virtual dielectric layers, and the grooves expose the substrate; forming sacrificial oxide layers on side walls of the grooves; removing the sacrificial oxide layers and oxide layers, on the surface layer of the semiconductor substrate, exposed at the bottom parts of the grooves; and forming semiconductor layers on the semiconductor substrate at the bottom parts of the grooves. The manufacturing method can protect the interlayer dielectric layers against damage, thus cannot enlarge the critical size of groove open holes, cannot influence the sidewall roughness of the groove open holes, and further improve the performance of the final device. The semiconductor device and the electronic device have better performance.