39results about How to "Increase critical size" patented technology

The invention provides a semiconductor structure and a manufacturing method thereof, and the method comprises the following steps: providing a stacked structure, and forming a first recessed structurein the stacked structure, wherein the first recessed structure extends downwards into an insulating medium interlayer but does not penetrate through an insulating medium interlayer; etching the insulating medium interlayer by taking a first hard mask layer as a mask to obtain a second concave structure in the stacked structure, wherein the second concave structure extends to the surface of the etching barrier layer and has a vertical side wall; transversely trimming the second hard mask layer to enlarge the size of a top opening of the second hard mask layer; and etching the insulating mediuminterlayer by taking the second hard mask layer as a mask so as to enlarge the opening size of the first concave structure in the insulating medium interlayer. The method can adapt to dual damascenehole patterns, slit patterns or groove pattern structures with different film thicknesses, and is beneficial to enlarging a processing window of chemical mechanical polishing of an insulating layer ina preorder process and enlarging a processing window of a key size at the bottom of a dual damascene hole.

The invention provides a semiconductor device and its manufacturing method and mask plate. In the manufacturing method of the semiconductor device, after forming a patterned core layer with a core on the gate dense area and the gate sparse area, the A sidewall is formed on the sidewall of the core, and then the gate layer is etched using the sidewall as a mask to form a first gate on the gate-dense region and a second gate on the gate-sparse region. When the gate base structure is used, the etching load effect between the gate dense area and the gate sparse area can be reduced or even completely avoided, and the uniformity of the critical dimension of the first gate in the formed gate dense area can be improved. The shape of the first gate at the edge is ensured, and then the tops of a plurality of adjacent second gate infrastructure structures on the gate sparse region are connected to form a second gate by means of a connecting gate layer.

The invention relates to an embedded flash memory, a preparation method thereof, and an electronic device. The method comprises that a substrate is provided, an active region isolated by a shallow trench isolation (STI) oxide is formed in the substrate, and the top of the STI oxide is higher than the surface of the substrate; a floating gate material layer is deposited to cover the active region and the STI oxide; the floating gate material layer is flattened to expose the surface of the STI oxide; the floating gate material layer is etched back to reduce the thickness of the floating gate material layer and expose the STI oxide of certain height; the exposed STI oxide is etched back to reduce the key size of the exposed STI oxide; the floating gate material layer is re-deposited till the top of the STI oxide to surround the STI oxide and flatten the floating material layer; and the part whose key size is reduced of the STI oxide is removed to form a T-shaped floating gate on the active region.

The invention provides a method for controlling the consistency of critical dimensions after an ultra-deep hole plasma etching process. The method for controlling the consistency of the critical dimensions after the ultra-deep hole plasma etching process comprises the following steps: introducing mixed gas into a reaction chamber after the ultra-deep hole plasma etching process, wherein the mixed gas comprises nitrogen, hydrogen and fluorine-containing gas; performing a plasma process on the reaction chamber into which the mixed gas is introduced. A metal copper layer which is accumulated on the wall of the reaction chamber is removed by introducing the mixed gas into the reaction chamber after the ultra-deep hole plasma etching process and performing the plasma process on the reaction chamber into which the mixed gas is introduced, wherein the mixed gas comprises the nitrogen, the hydrogen and the fluorine-containing gas. Therefore, the problem of etching rate drift of an oxide layer after the ultra-deep hole plasma etching process is avoided / lightened; the consistency of the critical dimensions of the ultra-deep hole plasma etching mass production process and the consistency of the formed integrated circuit devices are improved.

The present invention provides a touch display panel, comprising: a first substrate; a thin film transistor disposed on the first substrate; a pixel electrode layer disposed on the thin film transistor, and the pixel electrode layer passes through a contact hole connected to the drain or source of the thin film transistor; the common electrode layer is arranged on the first substrate and under the pixel electrode layer, and the common electrode layer is divided into a plurality of common electrodes adjacent to each other. Slits are formed between the common electrodes, and the slits are connected to the contact holes above the slits. The touch display panel provided by the invention improves touch detection capability and display effect.

The invention discloses a germanium-silicon triode base region hard mask membrane layer structure, which comprises a silicon chip, wherein a collector region and a field isolation region are arranged on the silicon chip; a polycrystalline silicon layer and a germanium-silicon membrane layer are grown on the collector region and the field isolation region, and the germanium-silicon membrane layer is partially grown above the polycrystalline silicon layer; and an inorganic anti-reflection material layer and at least one hard mask membrane layer are grown above the germanium-silicon membrane layer. The invention further discloses a manufacturing method of the germanium-silicon triode base region hard mask membrane layer structure. Through adoption of the germanium-silicon triode base region hard mask membrane layer structure, the influence of a germanium-silicon membrane layer diffuse reflection beam to the appearance of the photoresist is reduced, the control acpability to key sizes in the production is improved, and photoetching patterns of small sizes are obtained.

The invention relates to a method for forming a dopant well and a method for forming an image sensor. The method for forming the dopant well comprises the following steps: forming a silicon oxide layer on a semiconductor substrate; etching a photoresist layer and a silicon oxide layer until the layers are exposed out of the semiconductor substrate after forming the photoresist layer on the siliconoxide layer, and defining the graphics of the dopant well; incinerating the photoresist layer until the layer is exposed out of the silicon oxide layer, and increasing the key dimension of the graphics of the dopant well; taking the photoresist layer and the silicon oxide layer as masks, implanting ions into the semiconductor substrate along the increased graphics of the dopant well, and formingthe dopant well of which the depth is in graded distribution; and removing the photoresist layer and the silicon oxide layer. The invention also provides the method for forming the image sensor. The invention can uniformly control the key dimension of the dopant well and simplifies processing steps.

The invention provides a forming method of a high-K metal grid. The method comprises the following steps of step 1: sequentially forming an interlayer dielectric layer, a TiO2 film layer and a polycrystalline silicon layer on a substrate; step 2: performing patterning on the interlayer dielectric layer, the TiO2 film layer and the polycrystalline silicon layer so as to form a pseudo grid electrode structure; forming a grid electrode side wall at the side edge of the pseudo grid electrode structure; step 3: depositing the interlayer electric dielectric materials on the periphery of the pseudo grid electrode structure; flattening the interlayer electric dielectric materials; step 4: removing the top polycrystalline silicon layer in the pseudo grid electrode structure to form a groove; step 5: performing Hf ion injection on the TiO2 film layer in the pseudo grid electrode structure so as to form an HfTiO film layer; step 6: filling metal materials into the groove so as to form the metal grid.